The message-driven processor: a multicomputer processing node with efficient mechanisms

Dally, William J.; Fiske, J.A.S.; Keen, John S.; Lethin, Richard; Noakes, Michael D.; Nuth, P.R.; Davison, R.; Fyler, G.

doi:10.1109/40.127581

Cited by 157 publications

(36 citation statements)

References 12 publications

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“…(Every processor has two neighbors in each dimension.) Similar practical architectures include two-dimensional rectangular meshes such as Intel's Paragon architecture [10] and three-dimensional meshes such as the MIT-Intel J-machine [6].…”

Section: B Nonbinary Cubesmentioning

confidence: 99%

On a new class of codes for identifying vertices in graphs

Karpovsky

Chakrabarty

Levitin

1998

IEEE Trans. Inform. Theory

379

321

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Abstract-We investigate a new class of codes for the optimal covering of vertices in an undirected graph G such that any vertex in G can be uniquely identified by examining the vertices that cover it. We define a ball of radius t centered on a vertex v to be the set of vertices in G that are at distance at most t from v: The vertex v is then said to cover itself and every other vertex in the ball with center v: Our formal problem statement is as follows: Given an undirected graph G and an integer t 1, find a (minimal) set C of vertices such that every vertex in G belongs to a unique set of balls of radius t centered at the vertices in C: The set of vertices thus obtained constitutes a code for vertex identification. We first develop topology-independent bounds on the size of C: We then develop methods for constructing C for several specific topologies such as binary cubes, nonbinary cubes, and trees. We also describe the identification of sets of vertices using covering codes that uniquely identify single vertices. We develop methods for constructing optimal topologies that yield identifying codes with a minimum number of codewords. Finally, we describe an application of the theory developed in this paper to fault diagnosis of multiprocessor systems.

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Section: B Nonbinary Cubesmentioning

confidence: 99%

On a new class of codes for identifying vertices in graphs

Karpovsky

Chakrabarty

Levitin

1998

IEEE Trans. Inform. Theory

379

321

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show abstract

“…In blocking thread models, such as HEP [35], Tera [1], Dash [40], Iannucci's Hybrid Architecture [16] and, to a certain extent, J-Machine [9], each thread can be suspended (or blocked) and then resumed, and hence the model requires a mechanism to save states and to move threads between different states. Hardware support may range from just queueing the suspended instruction to saving a set of registers.…”

Section: Related Workmentioning

confidence: 99%

Generation, Optimization, and Evaluation of Multithreaded Code

Roh

Najjar

Böhm

1996

Journal of Parallel and Distributed Computing

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“…With persistent stream links and these instructions added to the processor's ISA, there is no need to spend extra cycles setting up a communication, specifying the destination, or formating a packet (for contrast, compare e.g., [35,20]). This approach integrates streaming communication into the processor abstraction, allowing it to be supported efficiently with hardware.…”

Section: Stream Opsmentioning

confidence: 99%