The microarchitecture of the IBM eServer z900 processor

Schwarz, E.; Check, M. A.; Shum, C.-L. K.; Kœhler, Thomas; Swaney, S. B.; MacDougall, J. D.; Krygowski, C. A.

doi:10.1147/rd.464.0381

Cited by 15 publications

(5 citation statements)

References 11 publications

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“…Decimal number system is among these systems. An example is the introduction of instruction support in hardware for decimal arithmetic in some recent processors [4]. Also, the proposed revision to the IEEE 754 standard for Floating Point (FP) arithmetic to include specifications for decimal arithmetic [9] is another case for the increase interest The QCA inverter can be implemented in different ways [6,14,16].…”

Section: Abstract-quantum-dot Cellular Automata Decimal Adder Arithmentioning

confidence: 99%

The design of Quantum-dot CellularAutomata decimal adder

Kharbash

Chaudhry

2008

2008 IEEE International Multitopic Conference

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Figure 1. QCA Cell and Wire II. QCA BASICSThe classical QCA cell and wire [16] are shown in fig. 1. Each QCA cell is composed of four quantum dots occupied by two electrons and separated by tunneling barriers. The electrons can tunnel between the dots, but not the cells. They are forced to occupy the cell coroner's positions due to Columbic repulsion to maximize their separation. This results in two stable configurations known as cell polarization P= +1 and P = -1. This configuration is used to represent binary logic where P = + 1 is used to represent the logic "1" and P = -1 is used to represent the binary logic "0". QCA operates by Coulombic interaction [16] that connects the state of one cell to the state of its neighbors. Thus, no electrical current is needed to transfer information. A QCA wire is created by an array of QCA cells where the neighboring QCA cells interact with each other which results in the information flow between them.in decimal arithmetic. With this revision currently in progress, it is likely that many high-end processors in the near future will perform decimal operations directly on decimal operations using dedicated decimal units that are much faster than the current decimal software packages [13].The addition operation is the basic operation in decimal arithmetic and it is carried out in hardware using Binary Coded Decimal adder also known as Decimal Adder. This adder is also the fundamental unit needed to design complex decimal units such as decimal floating point adders and multipliers. Thus, it is important to explore the decimal design in future nanotechnologies. To the best of our knowledge, this is the first design of QCA decimal adder using MVG. The reminder of this work is organized as follows. In Section II, we give some background material on QCA. The design of the proposed QCA decimal adder is presented in section III. Then discussed and analyzed in Section IV. This is followed by the paper conclusion.Abstract-Recently, there has been an increasing interest in hardware support for decimal arithmetic driven by the growing demands from financial and commercial applications. A crucial building block for decimal operations is the decimal adder. Thus, it is important to explore its design in future nanotechnologies. This work presents the first decimal adder design in Quantumdot Cellular Automata (QCA) nanotechnology using majority voting gates. The proposed one-digit QCA decimal full adder structure in this paper requires 27 majority voting gates and 16 inverters.

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Section: Abstract-quantum-dot Cellular Automata Decimal Adder Arithmentioning

confidence: 99%

The design of Quantum-dot CellularAutomata decimal adder

Kharbash

Chaudhry

2008

2008 IEEE International Multitopic Conference

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“…In the recurrence (1), the dividend and the divisor are two normalized binary numbers in the range and is the number of iterations needed to produce the bits of the precision. Also, represents the quotient digit in the signeddigit (SD) redundant format [22] selected from the redundant radix-digit set (2) where and . In (1), the next partial remainder (PR),…”

Section: High-radix Srt Divisionmentioning

confidence: 99%

“…The ENIAC, which became operational in 1945 at the University of Pennsylvania, was one of the early attempts to use radix 10 calculations in digital computers [1]. The IBM eServer z900 seems to be the only recent processor capable of performing decimal instructions in hardware [2], [3]. However, its decimal computation capability is limited to integers operands.…”

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confidence: 99%

Fast Decimal Floating-Point Division

Nikmehr

Phillips

Lim

2006

IEEE Trans. VLSI Syst.

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“…Prior CMOS IBM mainframe processors [1][2][3][4] had a relatively simple microarchitecture and were optimized for traditional applications that ran on them. These applications tended to fully exploit the complex instructions in the z/Architecture* instruction set [5,6]; a significant number were written in assembly language (or at least used it for performance-critical routines); and they stressed the storage subsystem.…”

Section: Introductionmentioning

confidence: 99%

The IBM eServer z990 microprocessor

Siegel¹,

Pfeffer²,

Magee³

2004

IBM J. Res. & Dev.

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The IBM eServer z990 microprocessor implements many features designed to give excellent performance on both newer and traditional mainframe applications. These features include a new superscalar instruction execution pipeline, highbandwidth caches, a huge secondary translation-lookaside buffer (TLB), and an onboard cryptographic coprocessor. The microprocessor maintains zSeries leadership in RAS (reliability, availability, serviceability) capabilities that include state-of-the-art error detection and recovery.

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The microarchitecture of the IBM eServer z900 processor

Cited by 15 publications

References 11 publications

The design of Quantum-dot CellularAutomata decimal adder

The design of Quantum-dot CellularAutomata decimal adder

Fast Decimal Floating-Point Division

The IBM eServer z990 microprocessor

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