The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7x scaling

Or-Bach, Zvi

doi:10.1109/3dic.2013.6702316

Cited by 8 publications

(1 citation statement)

References 10 publications

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“…Main drawback of these technologies is that they are not shrinking at the same speed as transistors are, making them somehow power hungry; moreover the more they will shrink, the more precision will be needed for chip to chip alignment. To reach the highest possible standard cell and tier to tier interconnect densities required for cost-effective chips, 3D sequential integration process [3][4] [5] (also known as Monolithic 3D or CoolCube TM ) is currently developed with main features being sequential fabrication of MOS layers and correlation of tier to tier interconnect size with process node allowing fine-grain 3D partitioning of designs. These particularities make it a durable opportunity to slow down next node design migration while still improving integration.…”

Section: Introductionmentioning

confidence: 99%

From 2D to Monolithic 3D

Billoint

Sarhan

Rayane³

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

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Design of conventional 2D integrated circuits is becoming more and more challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number of design rules, transistor characteristics, variability and back end properties coupled with a constant need for a higher integration of functions / peripherals are creating an increasingly complex equation to solve for designers. Moving to the next node and taking advantage of the technology are now far from being straightforward as time to market has never been so short for industry. In order to overcome or at least postpone the time when we'll have to face the "next node migration constraints", a possible solution could be staying at the same node and go 3D with possible benefits such as wire length reduction, power savings and increased operating frequency. Since more than ten years now, interconnect technologies like Through Silicon Via (TSV), High Density (HD)-TSV and Copper to Copper (Cu-Cu) have arisen to take advantage of this possible 3-dimensional physical implementation with proofs of concept [1] or more recently industrial products [2]. Main drawback of these technologies is that they are not shrinking at the same speed as transistors are, making them somehow power hungry; moreover the more they will shrink, the more precision will be needed for chip to chip alignment. To reach the highest possible standard cell and tier to tier interconnect densities required for cost-effective chips, 3D sequential integration process [3][4][5] (also known as Monolithic 3D or CoolCube TM ) is currently developed with main features being sequential fabrication of MOS layers and correlation of tier to tier interconnect size with process node allowing fine-grain 3D partitioning of designs. These particularities make it a durable opportunity to slow down next node design migration while still improving integration. To fully benefit from CoolCube TM technology, a whole new way of designing circuits, from synthesis to place and route, will be required as some new challenges will arise. The point of this presentation is to show the possible use and limitations of the aforementioned technologies with a focus on Monolithic 3D and to give some insights about market expectations, challenges and available design techniques.

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Section: Introductionmentioning

confidence: 99%