The NAPA adaptive processing architecture

Rupp, Charlé R.; Landguth, M.; Garverick, T.; Gomersall, Edson; Holt, Hamish; Arnold, Jeffrey M.; Gokhale, Maya

doi:10.1109/fpga.1998.707878

Cited by 92 publications

(47 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Medium-grained architectures include NAPA [10]. In NAPA, the Adaptive Logic Processor (ALP) can access the same memory space as the Fixed Instruction Processor (FIP), so the communication overhead between the ALP and the FIP is reduced compared with the coarse-grained architectures, but this approach still does not give the ALP full access to the register file.…”

Section: Prior Workmentioning

confidence: 99%

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Zhang

Martonosi

2000

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one can "design" a better instruction set when considering only a single application than when considering a general collection of applications. Configurable hardware gives us the opportunity to explore this option. This paper examines the potential for automatically identifying application-specific extended instructions and implementing them in programmable functional units based on configurable hardware. Adding fine-grained reconfigurable hardware to the datapath of an out-of-order issue superscalar processor allows 4-44% speedups on the MediaBench benchmarks [1]. As a key contribution of our work, we present a selective algorithm for choosing extended instructions to minimize reconfiguration costs within loops. Our selective algorithm constrains instruction choices so that significant speedups are achieved with as few as 4 moderately sized programmable functional units, typically containing less than 150 look-up tables each.

show abstract

Section: Prior Workmentioning

confidence: 99%

Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Zhang

Martonosi

2000

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…A processor is inserted near reconfigurable resources to configure them and to execute irregular processes. Performances can also be increased by exploiting the control parallelism thanks to tight coupling (Matrix [16], Chimaera [17], NAPA [18], etc. ).…”

Section: Introductionmentioning

confidence: 99%

An Auto-adaptative Reconfigurable Architecture for the Control

Ventroux

Chevobbe

Blanc

et al. 2004

Advances in Computer Systems Architecture

View full text Add to dashboard Cite

Abstract. Previous works have shown that reconfigurable architectures are particularly well-adapted for implementing regular processing applications. Nevertheless, they are inefficient for designing complex control systems. In order to solve this drawback, microprocessors are jointly used with reconfigurable devices. However, only regular, modular and reconfigurable architectures can easily take into account constant technology improvements, since they are based on the repetition of small units. This paper focuses on the self-adaptative features of a new reconfigurable architecture dedicated to the control from the application to the computation level. This reconfigurable device can itself adapt its resources to the application at run-time, and can exploit a high level of parallelism into an architecture called RAMPASS.

show abstract

“…Some of these projects, like OARP [9] or NAPA [12], associate a reconfigurable circuit to a programmable processor or controller. Furthermore, other architectures such as Piperench [6] or RAPID [4] can be reconfigured at a higher level in a more efficient way, respectively at the operator and at the functional level.…”

mentioning

confidence: 99%