Augmenting Modern Superscalar Architectures with Configurable Extended Instructions

Abstract

Abstract. The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one can "design" a better instruction set when considering only a single application than when considering a general collection of applications. Configurable hardware gives us the opportunity to explore this option. This paper examines the potential for automatically identifying application-specific extended instructions and implementing them in programmable functional units based on configurable hardware. Adding fine-grained reconfigurable hardware to the datapath of an out-of-order issue superscalar processor allows 4-44% speedups on the MediaBench benchmarks [1]. As a key contribution of our work, we present a selective algorithm for choosing extended instructions to minimize reconfiguration costs within loops. Our selective algorithm constrains instruction choices so that significant speedups are achieved with as few as 4 moderately sized programmable functional units, typically containing less than 150 look-up tables each.

Factors Influencing the Performance of a CPU-RFU Hybrid Architecture

“…The T1000 architecture [14] is an extension of the PRISC, although the CPU is a superscalar processor. The focus of this work is on developing a selective algorithm that is used to extract RFUops.…”

Designing a runtime reconfigurable processor for general purpose applications

“…Furthermore, the programmer has either to invoke pre-compiled hardware libraries that implement specialized functions or tasks in hardware, or he has to encode himself the respective compute-intensive tasks in hardware and to map them to the reconfigurable processing units. This kind of computing has been tested with reported performance benefits in the following projects: PRISC [11], DISC [16], CoMPARE [13], GARP [5], OneChip [3], T1000 [19] etc. All these configurable processors support the conventional way of sequencing instructions.…”

Peer-to-peer hardware-software interfaces for reconfigurable fabrics

“…¢ Systems such as PRISC [6], Chimaera [5,13] and T1000 [14] use a custom-instruction style of interface between the CPU and the RFU. A custom instruction is a RISC-like instruction whose opcode indicates an RH configuration that carries the computation.…”