Abstract

Abstract

In this paper we examine the opportunities brought about by recent progress in electronic nanotechnologyMoore's law has been equated with a guaranteed stream of good news, bringing ever higher clock speeds and more hardware resources in each new hardware generation. Microarchitects have been significant beneficiaries, building faster processors and using more resources to exploit program parallelism. However, significant difficulties loom for the traditional approach to processor design.Traditional microarchitectures are monolithic in nature, as their component structures are tightly dependent on each other. Such designs are not scalable with the increasing amount of resources, and are already stretched to their limits. Approaches that aim at decoupling the components, but remain tied to previous architectural structures, introduce overhead and additional complexity.Recent advances in molecular electronics, combined with increased challenges in semiconductor manufacturing, create a new opportunity for computer architects -the opportunity to recreate computer architecture from the ground up. New device characteristics require us to rethink the basic abstraction of the transistor. New fabrication methods require us to rethink the basic circuit abstraction. The scale of the devices and wires allows us to rethink our basic approach to designing computing systems. On the one hand, the scale enables huge computing systems with billions of components. On the other hand, the scale forces us to rethink the meaning of a working system; it must be a reliable system made from unreliable components.Computer architecture builds computing systems as hierarchies of abstractions. Molecular computing may be a case where a reexamination of the layers of abstraction is required. In this paper we propose an alternative computer system architecture, based on dramatically different abstractions:

No abstract

In this paper we describe a peer-to-peer interface between processor cores and reconfigurable fabrics. The main advantage of the peer-to-peer model is that it greatly expands the scope of application for reconfigurable computing and hence its potential benefits. The primary extension in our model is that "code" on the reconfigurable hardware unit is allowed to invoke routines both on the reconfigurable unit itself and on the fixed logic processor. We describe the software constructs and compilation mechanisms needed for such an architecture, including a detailed description of the interface between the two parts of the application.