The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications

Scholten, A.J.; Smit, G.D.J.; Vries, B.A. De; Tiemeijer, L.F.; Croon, J.A.; Klaassen, D.B.M.; Langevelde, R. van; Li, Xin; Wu, Weimin; Gildenblat, G.

doi:10.1109/jssc.2009.2015821

Cited by 23 publications

(17 citation statements)

References 25 publications

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“…19(b) is compared with the optimal estimated by (13),which shows the good accuracy of our model. As suggested by (12), for small the distortion generated by is much larger than that from . Therefore, IIP3 is determined by .…”

Section: Common-gate Lna Linearity Optimizationmentioning

confidence: 90%

“…All simulations are done in Spectre circuit simulator, using the PSP compact MOSFET model [18] fitted to our 90 nm CMOS process. The PSP model is known to correctly fit derivatives up to the third order [12], [13] and to satisfy the so-called Gummel symmetry test (GST) [14], [15]. Fitting derivatives up to the third order is essential to reliably estimate distortion levels for all presented circuits in this paper.…”

Section: Simplifying the Transistor Nonlinearity Modelmentioning

confidence: 99%

“…18. This allows for simplification of (10) into (11) To the first order approximation, the is inversely proportional to the transistor width and the third-order output conductance nonlinearity is proportional to , we use and which yields (12) From (12) it follows that:…”

Section: Common-gate Lna Linearity Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model

Cheng

Alink

Annema

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper focuses on optimizing the linearity in known RF circuits, by exploring the circuit design space that is usually available in today's deep submicron CMOS technologies. Instead of using brute force numerical optimizers we apply a generalized weak nonlinearity model that only involves AC transfer functions to derive simple equations for obtaining design insights.The generalized weak nonlinearity model is applied to three known RF circuits: a cascode common source amplifier, a common gate LNA and a CMOS attenuator. It is shown that in deep submicron CMOS technologies the cascode transistor in both the common source amplifier and in the common gate amplifier significantly contributes IM3 distortion. Some design insights are presented for reducing the cascode transistor related distortion, among which moderate inversion biasing that improves IIP3 by 10 dB up to 5 GHz in a 90 nm CMOS process. For the attenuator, a wideband IM3 cancellation technique is introduced and demonstrated using simulations.

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Section: Common-gate Lna Linearity Optimizationmentioning

confidence: 90%

Section: Simplifying the Transistor Nonlinearity Modelmentioning

confidence: 99%

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RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model

Cheng

Alink

Annema

et al. 2012

IEEE Trans. Circuits Syst. I

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“…These models excelled in accuracy through many generations Manuscript of technology from 350 to 28 nm [2]. While BSIM3 and BSIM4 are threshold-based models, there also exist different class of models based on surface potential approach [3], [4] and charge-based approach [5]. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Chauhan

Venugopalan

Chalkiadaki

et al. 2014

IEEE Trans. Electron Devices

123

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BSIM6 is the latest industry-standard bulk MOS-FET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

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“…Let us consider a DC circuit containing short channel MOS transistors, characterised by a PSP model [6,8,12,16,28]. Each power supply source is represented by a current source and a resistor connected in parallel; thus we will be able to apply the standard nodal method for the circuit description.…”

Section: Preliminariesmentioning

confidence: 99%

A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits

Tadeusiewicz

Hałgas

2013

Circuits Syst Signal Process

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This paper is devoted to the analysis of CMOS transistor circuits, fabricated in nanometer technology, having multiple DC operating points. The MOS transistors are characterised by the intricate PSP 103.1.1 model elected by the CMC as a standard. To find the operating points an approach is proposed based on a mathematical concept called a deflation. According to this concept the equations describing the circuit are deformed to avoid the solutions earlier determined and retain the remaining solutions. A new efficient deflation technique is developed and combined with the homotopy method and the discrete circuit equivalent of the Newton-Raphson nodal analysis. An algorithm has been worked out for finding multiple DC operating points of CMOS circuits encountered in practical applications. To illustrate the proposed approach three numerical examples are given.

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The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications

Cited by 23 publications

References 25 publications

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model

RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model

BSIM6: Analog and RF Compact Model for Bulk MOSFET

A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits

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