2009
DOI: 10.1016/j.measurement.2009.05.004
|View full text |Cite
|
Sign up to set email alerts
|

The new method of calculation sum and difference histogram for quantized data

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

1
12
0

Year Published

2012
2012
2018
2018

Publication Types

Select...
5
1

Relationship

1
5

Authors

Journals

citations
Cited by 12 publications
(13 citation statements)
references
References 5 publications
1
12
0
Order By: Relevance
“…The mathematical model of averaging for both synchronous and asynchronous measurements is presented. The results of simulations for asynchronous measurements correspond to theoretical approaches presented in [9][10][11][12], but are significantly more general. In case of synchronous measurements, the model allows to research the influence of different types of noise on results of averaging.…”
Section: Discussionsupporting
confidence: 77%
“…The mathematical model of averaging for both synchronous and asynchronous measurements is presented. The results of simulations for asynchronous measurements correspond to theoretical approaches presented in [9][10][11][12], but are significantly more general. In case of synchronous measurements, the model allows to research the influence of different types of noise on results of averaging.…”
Section: Discussionsupporting
confidence: 77%
“…The quantization and nonlinearity minimization method (QNM) assumed the usage (as the PDF function) of the continuous uniform distribution for every quantized data [7]. The width of this distribution is equal to the range of the time channel (quantization step) where time stamp has been receipted.…”
Section: Principle Of the Scm Methodsmentioning
confidence: 99%
“…[8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time. [21][22][23][24][25][26][27] The tapped delay line (TDL) is the simplest TDC architecture. [17][18][19][20] However, a lack of uniformity in the delay cell of FPGA-based TDC implementations lowers the time resolution.…”
Section: Introductionmentioning
confidence: 99%
“…Thus, numerous studies have attempted to deal with the nonuniformity in the delay cell of FPGA platforms by using calibration circuits. [21][22][23][24][25][26][27] Wave-union TDCs improve the time resolution, particularly in the ultra-wide bins found in FPGA-based TDCs. 28 Uniform delay cells are required for a TDL TDC.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation