The NUMAchine multiprocessor

Grindley, R.; Abdelrahman, Tarek S.; Brown, Stephen D.; Caranci, S.; DeVries, Derek J.; Gamsa, Benjamin; Grbic, A.; Gusat, Mitch; Ho, Richard C.; Krieger, Orran; Lemieux, Guy; Loveless, Kelvin; Manjikian, Naraig; McHardy, Paul; Srbljic, S.; Stumm, Michael; Vranesic, Z.G.; Žilić, Željko

doi:10.1109/icpp.2000.876165

Cited by 37 publications

(24 citation statements)

References 45 publications

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“…The use of this topology was inspired by a NUMAchine multiprocessor designed at University in Toronto. As shown in [18], good speedups were observed for virtually all multiprocessor benchmarks, in spite of its apparent bisectional bandwidth limitations. The architecture was shown amenable to efficient implementations, and the cache coherence protocol incorporated in NUMAchine exploited well the given topology resulting in a feasible and correct implementation.…”

Section: Related Workmentioning

confidence: 85%

“…Because the buses are used at the lowest level of the hierarchy in [18], the total number of nodes will be kept modest if the number of hierarchy levels is kept low. By replacing local buses with meshes, we can accommodate more processors for the same hierarchical ring.…”

Section: B Suitability Of Hierarchical Ringsmentioning

confidence: 99%

“…By replacing local buses with meshes, we can accommodate more processors for the same hierarchical ring. Similarly to [18], we aim to use the concept of the network cache placed at the gateways to rings, to facilitate efficient cache coherency primitives, including the use of low-cost multicast/broadcast invalidations with guaranteed serialization property, which is in turn critical for both cache coherence and the useful consistency models.…”

Section: B Suitability Of Hierarchical Ringsmentioning

confidence: 99%

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A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Bourduas

Žilić

2007

First International Symposium on Networks-on-Chip (NOCS'07)

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Abstract-A popular network topology for Network-on-Chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring/mesh architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count.

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Section: Related Workmentioning

confidence: 85%

Section: B Suitability Of Hierarchical Ringsmentioning

confidence: 99%

Section: B Suitability Of Hierarchical Ringsmentioning

confidence: 99%

See 1 more Smart Citation

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Bourduas

Žilić

2007

First International Symposium on Networks-on-Chip (NOCS'07)

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“…In future, this work can be expanded for incorporation with multiprocessor design [41][42] [43], for enhancing debug features [44], in reliable networks on chip [45][46], as well as reversible [47], embedded high-density memory [48] design, and the extension is possible with transform-based techniques under lack of available data [49]. Finally, the low-power [50] and the sequential design test [51] can be applied.…”

Section: Future Workmentioning

confidence: 99%

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Najafi

Banville²,

Hafed³

et al. 2013

Analog Integr Circ Sig Process

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High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This thesis investigates techniques to speed up bit-error rate (BER) and jitter testing of HSSI devices.This work proposes an oversampling-based transmitter test scheme that accelerates transmitter jitter as well as eye diagram testing through the deployment of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed.We aim to accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds. This exceeds the performance of [2], which by itself was an improvement from seconds to 100 ms.ii

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“…As commercial CMPs continue to increase core counts, a new network design will be needed that balances the simplicity and low overhead of rings with the scalability of more complex topologies. [43,51,21,44,19] allows "local rings" with simple node routers to scale by connecting to a "global ring" via bridge routers.…”

Section: Introductionmentioning

confidence: 99%

Design and Evaluation of Hierarchical Rings with Deflection Routing

Ausavarungnirun

Fallin

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by reintroducing more complex in-ring buffering and buffered flow control. Our goal in this paper is to design a new hierarchical ring interconnect that can maintain most of the simplicity of traditional ring designs (i.e., no in-ring buffering or buffered flow control) while achieving high scalability as more complex buffered hierarchical ring designs.To this end, we revisit the concept of a hierarchical-ring networkon-chip. Our design, called HiRD (Hierarchical Rings with Deflection), includes critical features that enable us to mostly maintain the simplicity of traditional simple ring topologies while providing higher energy efficiency and scalability. First, HiRD does not have any buffering or buffered flow control within individual rings, and requires only a small amount of buffering between the ring hierarchy levels. When inter-ring buffers are full, our design simply deflects flits so that they circle the ring and try again, which eliminates the need for in-ring buffering. Second, we introduce two simple mechanisms that together provide an end-to-end delivery guarantee within the entire network (despite any deflections that occur) without impacting the critical path or latency of the vast majority of network traffic.Our experimental evaluations on a wide variety of multiprogrammed and multithreaded workloads and synthetic traffic patterns show that HiRD attains equal or better performance at better energy efficiency than multiple versions of both a previous hierarchical ring design and a traditional single ring design. We also extensively analyze our design's characteristics and injection and delivery guarantees. We conclude that HiRD can be a compelling design point that allows higher energy efficiency and scalability while retaining the simplicity and appeal of conventional ring-based designs.

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The NUMAchine multiprocessor

Abstract: Abstract

Cited by 37 publications

References 45 publications

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Design and Evaluation of Hierarchical Rings with Deflection Routing

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