The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

Wu, Meile; Jin, Xiaoshi; Kwon, Hyuck‐In; Chuai, Rongyan; Liu, Xi; Lee, Jong-Ho

doi:10.5573/jsts.2013.13.3.245

Cited by 34 publications

(14 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For more than a decade, Moore's law has been an ultimate guideline for MOSFET minituarization. The main obstacle of shrinking the dimension of MOSFET is the decrease in gate controllability over the channel due to high electric field [1][2][3][4]. An alternative solution to improve the gate control over the channel is by adding an extra gate [5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2019

IJECE

View full text Add to dashboard Cite

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

show abstract

Section: Introductionmentioning

confidence: 99%

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2019

IJECE

View full text Add to dashboard Cite

show abstract

“…Junctionless configuration is another alternative solution to allow the continuity of transistor's shrinkage without degrading the device performance [35][36][37][38]. This configuration has been aggressively studied and applied by many researchers due to its simplified fabrication process [39].…”

Section: Introductionmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

View full text Add to dashboard Cite

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

show abstract

“…2,3 The geometry and material of gate in JL FETs have been modulated to obtain a better performance by changing the degree of energy band bending which is able to suppress the band-to-band tunneling. 4,5 Some groups have also done a lot of research about the adjustments of gate spacer dielectric to decrease leakage current and improve analog characteristics. [6][7][8] Nevertheless, when the gate length is continuously reduced to extremely deep nanoscale (less than 15 nm, for example), the subthreshold properties of JL FETs will deteriorate again.…”

Section: Introductionmentioning

confidence: 99%

A novel low leakage saddle junctionless FET with assistant gate

Jin

Gao

Yang

et al. 2018

Int J Numerical Modelling

Self Cite

View full text Add to dashboard Cite

In this paper, a novel low leakage saddle junctionless field effect transistor with assistant gate is proposed. Its electrical properties have been extensively investigated by studying the influence resulting from variation of design parameters, such as the thickness of assistant gate, oxide layer thickness between the main and assistant gate, extension height of S/D contact, and the voltage of assistant gate. Compared with conventional structure, the proposed saddle junctionless field effect transistor with assistant gate shows much better performance at off state. The leakage current is effectively restrained, and the I on -I off ratio is largely improved. Design parameter optimization has also been performed.

show abstract

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

Cited by 34 publications

References 9 publications

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

A novel low leakage saddle junctionless FET with assistant gate

Contact Info

Product

Resources

About