The performance of source-coupled FET logic circuits that use GaAs MESFETs

Vu, T.T.; Peczalski, A.; Lee, K.W.; Conger, J.

doi:10.1109/4.288

Cited by 11 publications

(2 citation statements)

References 22 publications

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“…6,7 At present, the DCFL configuration offers many advantages over other logic family members, such as buffered FET logic (BFL) and source coupled FET logic (SCFL). 8,9 The fabrication of D/E-mode integrated HEMTs on same substrate is important for the requirement of the precise etching control of the Schottky layer thickness to determine the essential device characteristics, such as current density, threshold voltage, and logic characteristic, etc. [10][11][12] Recently, we have demonstrated the improved gate characteristics of the AlGaAs/InGaAs E-mode pseudomorphic HEMTs (PHEMTs) by way of hybrid gate recesses to remove the n-AlAs/i-GaAs/n-AlGaAs virtual channel layers upon 2DEG channels.…”

mentioning

confidence: 99%

Inverter Logic of AlGaAs/InGaAs Enhancement/Depletion-Mode Pseudomorphic High Electron Mobility Transistors with Virtual Channel Layers

Tsai¹,

Lin²,

Lour³

et al. 2019

ECS J. Solid State Sci. Technol.

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In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.

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confidence: 99%

Inverter Logic of AlGaAs/InGaAs Enhancement/Depletion-Mode Pseudomorphic High Electron Mobility Transistors with Virtual Channel Layers

Tsai¹,

Lin²,

Lour³

et al. 2019

ECS J. Solid State Sci. Technol.

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“…The proposed sampling circuit needs a good control of delays that may consequently not vary with process and ambient variations. This imposes the use of less sensitive gates to these variations, as is the case of the SCFL gates due to its differential nature (Vu, 1988;De Marco, 1996). These differential gates are also less susceptible to noise, which will result in smaller jitter.…”

Section: Description and Design Of The Sampling Circuitmentioning

confidence: 99%

A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates

Marco

Noije²,

Swart

1997

VLSI: Integrated Systems on Silicon

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This paper presents the implementation of the sampling technique by means of the coordinated delays' method, using the SCFL (Source Coupled FET Logic) logic in GaAs MESFET technology. This technique presents a high resolution and is based on controlling delays in the clock and in the data signal paths, by means of delay elements. The resolution is related to the difference in the delay in both paths. The delay elements are implemented by means of differential invertors, in SCFL logic. A sample circuit of 64 stages has been designed. Its operation has been simulated using the HSPICE program that resulted in a high resolution at a bit rate of 3.33 Gb/s. The circuit prototypes are being fabricated at Vitesse Semiconductor, using the H-GaAs III process with 0.6Jlm gate length. Measurement results "like maximum rate, resolution and jitter" will be presented at the meeting.

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