2011
DOI: 10.1007/s10766-011-0172-7
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The Performance Optimization of Threaded Prefetching for Linked Data Structures

Abstract: Helper threaded prefetching based on Chip Multiprocessor is a well known approach to reducing memory latency and has been explored in linked data structures accesses. However, conventional helper threaded prefetching often suffers from useless prefetches and cache thrashing, which affect its effectiveness. In this paper, we first analyzed the shortcomings of conventional helper threaded prefetching for linked data structures. Then we proposed an improved helper threaded prefetching, Skip Helper Threaded Prefet… Show more

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Cited by 6 publications
(13 citation statements)
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References 35 publications
(45 reference statements)
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“…1a shows that a majority of last-level cache misses are caused by the second level traversals in inner for-loop. As indicated in our earlier works [20,28], for LDS programs with low CALR, the helper thread may be too stressed to run ahead of the main thread, thus making no performance gain. Nonetheless, this problem can be solved if the helper thread ignores some problem loads.…”
Section: Shtp Mechanismmentioning
confidence: 95%
See 4 more Smart Citations
“…1a shows that a majority of last-level cache misses are caused by the second level traversals in inner for-loop. As indicated in our earlier works [20,28], for LDS programs with low CALR, the helper thread may be too stressed to run ahead of the main thread, thus making no performance gain. Nonetheless, this problem can be solved if the helper thread ignores some problem loads.…”
Section: Shtp Mechanismmentioning
confidence: 95%
“…The selection of proper R P has been illustrated in our earlier work [28]. The right R P can improve the parallelism of helper thread and main thread.…”
Section: R P Tune With Calrmentioning
confidence: 99%
See 3 more Smart Citations