The POWER2 performance monitor

Welbon, E.H.; Chan-Nui, C. C.; Shippy, D.; Hicks, D. A.

doi:10.1147/rd.385.0545

Cited by 27 publications

(9 citation statements)

References 9 publications

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“…The optimization will be verified through actual execution. For this, performance counters [7,16] will be used to provide performance metrics like number of cache misses and the CPU cycles.…”

Section: Discussionmentioning

confidence: 99%

Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Tao

Karl

2006

Proceedings of the 1st International Conference on Performance Evaluation Methodolgies and Tools - Valuetools '06

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Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the side of programmers or compilers with code level optimization or at system level through appropriate schemes, like reconfigurable cache organization and adequate prefetching or replacement strategies. For the former users need to know the problem, the reason, and the solution, while for the latter a platform is required for evaluating proposed and novel approaches.As existing simulation systems do not provide such information and platforms, we implemented a cache simulator that models the complete cache hierarchy and associated techniques. More specifically, it analyzes the feature of cache miss and provides information about the runtime accesses to data structures and the cache access behavior. Together with a visualization tool, this information enables the user to detect access hotspots and optimization strategies for tackling them. For supporting the study of different techniques with respect to cache configuration and management, this simulator models a variety of cache line replacement and prefetching policies, and allows the user to specify any cache organization, including cache size, cache set size, block size, and associativity. The simulator hence forms a research platform for investigating the influence of these techniques on the execution behavior of applications.

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Section: Discussionmentioning

confidence: 99%

Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Tao

Karl

2006

Proceedings of the 1st International Conference on Performance Evaluation Methodolgies and Tools - Valuetools '06

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“…On-chip performance counters [18,19] have been used for performance evaluation and tuning of parallel applications. They have been used on an IBM SP2 distributed memory multicomputer system [18] and a SGI Origin2000 distributed shared memory multiprocessor system for tuning and characterization of Computational Fluid Dynamics applications [16].…”

Section: Related Workmentioning

confidence: 99%

“…They have been used on an IBM SP2 distributed memory multicomputer system [18] and a SGI Origin2000 distributed shared memory multiprocessor system for tuning and characterization of Computational Fluid Dynamics applications [16]. All of these efforts are primarily focused on application tuning and use processor level measurements as a tool to facilitate the process of identifying bottlenecks in application code.…”

Section: Related Workmentioning

confidence: 99%

Performance characterization of multi-thread and multi-core processors based XML application oriented networking systems

Ding

Waheed

Yao

et al. 2010

Journal of Parallel and Distributed Computing

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“…In 1992, the RISC System/6000 POWER2* [2] processor, which we refer to as the "P2," had 22 counters integrated in four units, which were implemented as separate chips. The P2 PM provided up to 16 groups for each unit.…”

Section: Evolution Of Performance Monitors In Power and Powerpc Procementioning

confidence: 99%

“…Reference [2] provides a description of the P2 PM and its intended use, while Reference [1] describes the 604 PM and details its intended use. Reference [3] also describes the 604 PM, including specific examples related to event sampling, thresholding, and symmetric multiprocessor (SMP) analysis.…”

Section: Use Of Tlie Pivimentioning

confidence: 99%

A programmer's view of performance monitoring in the PowerPC microprocessor

Levine

Roth²

1997

IBM J. Res. & Dev.

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Performance monitor (PM) support in on-ciiipPowerPC® microprocessors is used to analyze processor, software, and system attributes for a variety of worlcloads. The interface to the PowerPC 604® microprocessor, which we abbreviate "604," has been externalized to end users. We discuss the enhanced PM support available in an upgrade of the 604, the PowerPC 604e™ microprocessor, which we abbreviate "604e." We discuss the challenges related to the externalization of the PM support as it relates to other PowerPC processors not derived from the 604 and briefly contrast these PMs with other PMs. We also describe an application programming interface (API) to the on-chip PM support, its design methodology, and its usage considerations, intended to meet these challenges.

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The POWER2 performance monitor

Cited by 27 publications

References 9 publications

Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Performance characterization of multi-thread and multi-core processors based XML application oriented networking systems

A programmer's view of performance monitoring in the PowerPC microprocessor

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