The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

Burgess, B.; Alexander, M.; Ho, Ying-Wai; Litch, S.; Mallick, S.; Ogden, D.; Park, Sungho; Slaton, J.

doi:10.1109/cmpcon.1994.282895

Cited by 19 publications

(2 citation statements)

References 2 publications

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“…Studies of instruction set design and its impact of cache performance and power consumption can be found in [1,3]. Studies of low power cache designs can also be found in [2,11]. This paper consists of five sections.…”

Section: Introductionmentioning

confidence: 99%

Cache design trade-offs for power and performance optimization

Despain

1995

Proceedings of the 1995 International Symposium on Low Power Design - ISLPED '95

249

151

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Section: Introductionmentioning

confidence: 99%

Cache design trade-offs for power and performance optimization

Despain

1995

Proceedings of the 1995 International Symposium on Low Power Design - ISLPED '95

249

151

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“…While the design of energy-aware hardware is critical [8], [9], the dynamic energy expended during execution of a given application depends on how different components are exercised by the application being run. For example, memory-sensitive compilation techniques [29] can increase the number of data accesses satisfied from on-chip memories with low capacitive loads instead of large offchip memories that present high capacitive loads to the system.…”

Section: Introductionmentioning

confidence: 99%

Access pattern restructuring for memory energy

Luz

Kadayif

Kandemir

et al. 2004

IEEE Trans. Parallel Distrib. Syst.

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Improving memory energy consumption of programs that manipulate arrays is an important problem as these codes spend large amounts of energy in accessing off-chip memory. In this paper, we propose a data-driven strategy to optimize the memory energy consumption in a banked memory system. Our compiler-based strategy modifies the original execution order of loop iterations in array-dominated applications to increase the length of the time period(s) in which memory banks are idle (i.e., not accessed by any loop iteration). To achieve this, it first classifies loop iterations according to their bank accesses patterns and then, with the help of a polyhedral tool, tries to bring the iterations with similar bank access patterns close together. Increasing the idle periods of memory banks brings two major benefits: first, it allows us to place more memory banks into low-power operating modes and, second, it enables us to use a more aggressive (i.e., more energy saving) operating mode (hence, saving more energy) for a given bank (instead of a less aggressive mode). The proposed strategy can reduce memory energy consumption in both sequential and parallel applications. Our strategy has been implemented in an experimental compiler using a polyhedral tool and evaluated using nine arraydominated applications on both a cacheless system and a system with cache memory. Our experimental results indicate that the proposed strategy is very successful in reducing the memory system energy and improves the memory energy by as much as 36.8 percent over a strategy that uses low-power modes without optimizing data access pattern. Our results also show that optimizations that target reducing off-chip memory energy can generate very different results from those that target at improving only cache locality.

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Scalable register file organisation for a multipleissue microprocessor

Kumar

1996

Electron. Lett.

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The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor

Cited by 19 publications

References 2 publications

Cache design trade-offs for power and performance optimization

Cache design trade-offs for power and performance optimization

Access pattern restructuring for memory energy

Scalable register file organisation for a multipleissue microprocessor

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