The prototype design of gFEX — a component of the l1calo trigger for the ATLAS phase-I upgrade

Chen, Hucheng; Begel, M.; Chen, Kai; Lanni, F.; Takai, H.; Tang, Shaochun; Wu, W.

doi:10.1109/nssmic.2016.8069899

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…Replacing traditional point-to-point links between front-end components and detector specific ROD (ReadOut Driver) systems, FELIX provides scalability, flexibility, uniformity and upgradability. In the ATLAS Run 3 upgrade, FELIX will be used by the Liquid Argon (LAr) Calorimeters, Level-1 Calorimeter trigger system, BIS 7/8 and the muon New Small Wheel (NSW) detectors, as shown in the figure 3 [12,13]. FELIX production board, as shown in the figure 4, is equipped with one 16lane PCIe Gen3 interface and eight onboard MiniPODs.…”

Section: Felixmentioning

confidence: 99%

Development of FELIX based readout system for HV-CMOS sensor testbeam

Chen

et al. 2019

J. Inst.

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The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration for the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. The HV-CMOS technology is a commercial integrated circuit process with the advantages of monolithic readout and fast charge collection. A front-end test platform of CaRIBOu (Control and Readout Itk BOard) and a testbeam Telescope based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, have been developed for the HV-CMOS sensor study and characterization in testbeam experiments. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between detector front-end electronics and the commodity switched network in the ATLAS upgrade. A FELIX based readout system has been developed for both the CaRIBOu and the testbeam Telescope. It has been deployed successfully in the testbeam at the CERN SPS H8 beamline in August 2017. The test results show that the readout system is capable of sensor calibration and readout of a high-density pixel detector with high trigger rate in testbeam experiments.

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Section: Felixmentioning

confidence: 99%

Development of FELIX based readout system for HV-CMOS sensor testbeam

Chen

et al. 2019

J. Inst.

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“…All the MGT links, including (optical links via MiniPODs and on board electrical traces), are running at 12.8 Gb/s stably without bit error. The on-board GTY electrical links have good eye diagram and are stable at 25.6 Gb/s without bit error [16]. The nine groups of 20-bit parallel GPIO data buses between two FPGAs have been tested running stably at 1.12 Gb/s in 560 MHz DDR mode with good margin (> 50%).…”

Section: Gfex Prototype V2mentioning

confidence: 99%

The implementation of Global Feature EXtractor (gFEX) - the ATLAS Calorimeter Level 1 Trigger system for LHC Run-3 upgrade

Tang¹,

Begel²,

Chen³

et al. 2018

J. Inst.

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As part of the ATLAS Phase-I Upgrade, the global Feature EXtractor (gFEX) is one of several hardware modules designed to help maintain the ATLAS Level-1 trigger acceptance rate with the increasing Large Hadron Collider (LHC) luminosity and the increasing Pile-Up conditions. The gFEX is used to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W & Z bosons, top quarks, and exotic particles in real time at the 40 MHz LHC bunch crossing rate. The board is required to receive coarse-granularity (Δη×Δφ = 0.2×0.2 gTower) information from the entire ATLAS calorimeters on 276 optical fibers. A prototype v1 with one Xilinx ZYNQ FPGA, and one Vertex-7 FPGA for technology validation has been designed and tested in 2015. With the lessons learned from the prototype v1, a prototype v2 with three Vertex UltraScale FPGAs and one ZYNQ FPGA has been implemented to verify full functionalities of gFEX in 2016. Based on the prototype v2 design, a prototype v3, the final gFEX prototype, is implemented, which is an ATCA module consisting of three Vertex UltraScale+ FPGAs, one ZYNQ UltraScale+ SoC, and 35 MiniPODs. This board receives up to 300 fiber optical links from calorimeters and transmits trigger data on 96 links to the to the ATLAS Level-1 Topological trigger (L1Topo [1]) at the speed up to 12.8 Gb/s. There are also 24 electrical links on board for communication between two FPGAs with the speed up to 25.6 Gb/s. The performance of three prototype boards have been tested and evaluated. For the prototype v3 board, the high-speed optical links are stable at 12.8 Gb/s with Bit Error Ratio (BER) < 1 × 10-15. The low-latency parallel GPIO (General Purpose I/O) buses between FPGAs are stable at 1.12 Gb/s. The peripheral components of ZYNQ UltraScale+ SoC, such as 16 GB DDR4 DIMM, UART, SPI flashes, and Ethernet, have also been verified. The test results of the prototype v3 board validate the gFEX technologies, architecture and full functionalities. Now the final production board is being produced.

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“…In total, 24 eFEX modules in two ATCA shelves and 7 jFEX modules in one ATCA shelf will be needed for the complete system. The gFEX [7] will receive 0.2 × 0.2 E T -sum data from the entire calorimeter in a single ATCA module, to identify large-radius jets and compute various global event observables. All of the FEXes will send results in the form of Trigger Objects (TOBs) to the Level-1 Topological Trigger Processor (L1Topo), and read out data to the Data Acquisition (DAQ) system, via optical links running at 12.8 Gb/s and 9.6 Gb/s, respectively.…”

Section: Introductionmentioning

confidence: 99%

The Phase-I Upgrade of the ATLAS First Level Calorimeter Trigger

Andrei

2018

Springer Proceedings in Physics

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The ATLAS Level-1 calorimeter trigger is planning a series of upgrades in order to face the challenges posed by the upcoming increase of the LHC luminosity. The trigger upgrade will benefit from new front-end electronics for parts of the calorimeter that provide the trigger system with digital data with a tenfold increase in granularity. This makes possible the implementation of more efficient algorithms than currently used to maintain the low trigger thresholds at much harsher LHC collision conditions. The Level-1 calorimeter system upgrade consists of an active and a passive system for digital data distribution, and three different Feature Extractor systems which run complex algorithms to identify various physics object candidates. The algorithms are implemented in firmware on custom electronics boards with up to four high speed processing FPGAs. The main characteristics of the electronic boards are a high input bandwidth, up to several TB/s per module, implemented through optical receivers, and a large number of on-board tracks providing up to 12.8 Gb/s high speed connections between the receivers and the FPGAs as well as between the FPGAs for data sharing. Prototypes have been built and extensively tested, to prepare for the final design steps and the production of the modules. The contribution will give an overview of the system and present the module designs and results from tests with the prototypes.

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The prototype design of gFEX — a component of the l1calo trigger for the ATLAS phase-I upgrade

Cited by 4 publications

References 5 publications

Development of FELIX based readout system for HV-CMOS sensor testbeam

Development of FELIX based readout system for HV-CMOS sensor testbeam

The implementation of Global Feature EXtractor (gFEX) - the ATLAS Calorimeter Level 1 Trigger system for LHC Run-3 upgrade

The Phase-I Upgrade of the ATLAS First Level Calorimeter Trigger

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