The reconfigurable arithmetic processor

Fiske, Stuart; Dally, William J.

doi:10.1145/633625.52404

Cited by 4 publications

(1 citation statement)

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“…In 1988, Fiske and Dally [34] introduced the Reconfigurable Arithmetic Processor (RAP), which contains 64 floating units connected by a switching network. More recently, Intel's Teraflops processor [35] connected 80 floating-point MAC units using a high-speed network on chip.…”

Section: Programmable Arrays Of Arithmetic Primitivesmentioning

confidence: 99%

Improving FPGA Performance for Carry-Save Arithmetic

Parandeh-Afshar

Verma

Brisk

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed through systematic data flow transformations that can be applied by a hardware compiler. Field-programmable gate arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the "field programmable counter array" (FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA as an alternative to DSP blocks. In addition to multiplication and multiply accumulation, the FPCA can accelerate more general carry-save operations, such as multi-input addition (e.g., add 2 integers) and multipliers that have been fused with other adders. Our experiments show that the FPCA accelerates a wider variety of applications than DSP blocks and improves performance, area utilization, and energy consumption compared with soft FPGA logic.Index Terms-Carry-save arithmetic, field-programmable gate array (FPGA), generalized parallel counter (GPC).

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Section: Programmable Arrays Of Arithmetic Primitivesmentioning

confidence: 99%