1AApproved for puh,ic rleas/. AbstractDitx iatf n U ti.ted...The J-Machine s a fine-grain concurrent computer that provides low-overhead jrimitive mechanisms for !ommunication, synchronization, and translation. Communicati )n mechanisms are provided that permit a node to send a message to any other nod in the machine in < 2p s. On message arrival, a task is created and dispatched in < 1 s. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed models of concurrent computation. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of memory, and a router. The nodes are connected by a high-speed 3-D mesh network. This design was chosen to make the most efficient use of available chip and board area. AbstractThe J-Machine is a fine-grain concurrent computer that provides low-overhead primitive mechanisms for communication, synchronization, and translation. Communication mechanisms are provided that permit a node to send a message to any other node in the machine in < 2ps. On message arrival, a task is created and dispatched in < ljis. A translation mechanism supports a global virtual address space. These mechanisms efficiently support most proposed nodels of concurrei t computation. The hardware is an ensemble of up to 65,536 nodes each containing a 36-bit processor, 4K 36-bit words of memory, and a router. The nodes are connected by a highspeed 3-D mesh network. This design was chosen to make the most efficient use of available chip and board area.

Artificial intelligence increasingly suffuses everyday life. However, people are frequently reluctant to interact with A.I. systems. This challenges both the deployment of beneficial A.I. technology and the development of deep learning systems that depend on humans for oversight, direction, and training. Previously neglected but fundamental, social-cognitive processes guide human interactions with A.I. systems. In five behavioral studies (N = 3,099), warmth and competence feature prominently in participants’ impressions of artificially intelligent systems. Judgments of warmth and competence systematically depend on human-A.I. interdependence. In particular, participants perceive systems that optimize interests aligned with human interests as warmer and systems that operate independently from human direction as more competent. Finally, a prisoner’s dilemma game shows that warmth and competence judgments predict participants’ willingness to cooperate with a deep learning system. These results demonstrate the generality of intent detection to interactions with technological actors. Researchers and developers should carefully consider the degree and alignment of interdependence between humans and new artificial intelligence systems.

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Laboratory Systems leven years ago, at ISCA 14, we published a paper titled, "Architecture of a Message-Driven Processor" [l] marking the start of our J-Machine project at MIT. The project culminated with the construction of a working prototype in 1991 [2] and the evaluation of this prototype in 1992 [12, 151. The J-Machine demonstrated the use of a jellybean part, a commodity part incorporating a processor, memory, and a fast communication interface, as a building block for computing systems. It was afine-grain parallel computer designed to exploit large amounts of parallelism by balancing the use of silicon area between processor and memory. The J-Machine provided a small set of efficient communication and synchronizationmechanisms that were used to support a broad range of programming models. It also provided fast user-to-user messaging without software intervention by having each message dispatch a message handler.This retrospective reviews the history of the J-Machine project, discusses its contributions with the perspective of hindsight, and assesses what was learned from the project

The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. It incorporates on one chip several serial, 64 bit floating point arithmetic units connected by a switching network. Hy sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units the RAP reduces the amount of off chip data transfer: in the examples we have simulated off chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. Simulations predict a peak performance of POMFlops with 800Mbit/sec off chip bandwidth in a 2pm CMOS process.