A DSP architecture optimized for wireless baseband

Rowen, Chris; Nuth, P.R.; Fiske, Stuart

doi:10.1109/socc.2009.5335658

Cited by 12 publications

(3 citation statements)

References 2 publications

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“…However in the case of high DLP algorithms our architecture has performances in the range of SIMD solutions. For example: Tensilica's DSP [8] computes a FIR operation (256 complex input) in about 520 clock cycles; a programmable baseband processor described in [22] performs the same operation in about 1,000 clock cycles. The performance of our solution is somewhere in the middle, performing a correlation point (FIR operation with 256 complex inputs) in 688 clock cycles (see Table 2).…”

Section: Cell Search Resultsmentioning

confidence: 99%

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Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC

Airoldi

Ahonen

Garzia

et al. 2010

J Sign Process Syst

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The performance of the W-CDMA cell search algorithm can be significantly improved using homogeneous general purpose Multi-Processor System-on-Chip (MPSoC) architectures. The application also scales well, as the number of processing nodes increases, allowing practical accelerations to become close to the theoretical maximum. In this work we describe a template MPSoC architecture based on multiprocessor computational clusters, called Ninesilica. Each Ninesilica consist of nine processing nodes based on COFFEE RISC architecture. MPSoC inter-and intra-cluster communication are enabled using hierarchical Network-on-Chip with dedicated point to point and broadcast communication services for better performance. Proposed template has been used to instantiate complete systems with one and four Ninesilica clusters, resulting in MPSoCs with respectively 9 and 36 computational nodes. The MPSoCs have been physically prototyped on a FPGA device, and the W-CDMA cell search algorithm has been mapped on both MPSoC platforms. The four Ninesilica MPSoC can execute

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Section: Cell Search Resultsmentioning

confidence: 99%

“…A similar approach is used by Tensilica in their ConnX Baseband Engine processor [8]. The processor uses a 3-way VLIW instructions set and supports 8-way SIMD operations.…”

Section: Introductionmentioning

confidence: 99%

Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC

Airoldi

Ahonen

Garzia

et al. 2010

J Sign Process Syst

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“…Developer can vectorize the program himself using ConnX BBE's data type and intrinsic function. In addition Xtensa C and C++ compiler can automatically do this vectorization with little or no human intervention ( Figure 4 [19].…”

Section: Connx Bbe By Tensilicamentioning

confidence: 99%

State of the art baseband DSP platforms for Software Defined Radio: A survey

Anjum

Ahonen

Garzia

et al. 2011

J Wireless Com Network

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Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

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