The Reconfigurable Instruction Cell Array

Khawam, S.; Nousias, I.; Milward, M.; Muir, M.; Arslan, Tughrul

doi:10.1109/tvlsi.2007.912133

Cited by 68 publications

(29 citation statements)

References 12 publications

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“…The switch reduces dynamic power for non timing critical logic and standby power for logic when it is not being used. The author reported lower energy up to 3.6 times than an ARM7 device, and up to 6 times lower energy than a C55X DSP, by using several power reduction techniques, such as register file elimination and efficient instruction fetch that are proposed for a coarse-grain reconfigurable cell-based architecture in [77] . Power-gating is applied to the switches in the routing resources to reduce static power and duplicate routing resources, that use either high or low Vdd, are used to reduce dynamic power in [78] .…”

Section: Power Reduction At Architecture-and Circuitlevel Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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-Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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Section: Power Reduction At Architecture-and Circuitlevel Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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“…In [30], energy-efficient modules for embedded components in FPGAs are introduced to reduce power by optimizing the number of connections between the module and the routing resources, and by using reduced supply voltage circuit techniques. In [27], several power reduction techniques, such as register file elimination and efficient instruction fetch, are proposed for a coarse-grain reconfigurable cell-based architecture; up to 3.6 times lower energy than an ARM7 device, and up to 6 times lower energy than a C55X DSP, is reported.…”

Section: Circuit-and Architecture-level Designmentioning

confidence: 99%

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Lamoureux

Luk

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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“…This is typically the most computationally intensive part of a standard Image Signal Processor (ISP). The filter was re-implemented on a reconfigurable instruction cell-based processor [5], using the C language. Software optimisation techniques were used to reduce the filter kernel into a single basic block, small enough to fit onto the target architecture in a single configuration context.…”

Section: Application To Streamingmentioning

confidence: 99%

“…Coarse-grained DRAs, such as instruction cell based computing architectures [5][6], provide a high degree of instruction chaining inside the core, by allowing arbitrary connections to be made between the various functional units via a configurable routing network. This allows quite complex data paths to be rendered onto the fabric and executed in a single configuration.…”

Section: Introductionmentioning

confidence: 99%

Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications

Muir

Arslan

Lindsay

2008

2008 Design, Automation and Test in Europe

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Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot be provided by custom ASIC solutions. Currently, reconfigurable processors tend to offer insufficient throughput for widespread use in streaming applications. This paper demonstrates how structural-level pipelining techniques can be applied to rapidly dynamically reconfigurable computing architectures, in order to increase throughput. This is done by automatically inserting registers into the data path of performance critical code sections that have already been optimised into a single configuration context. A new algorithm is presented to choose the insertion point of pipeline stage registers in order to meet a specified throughput whilst minimising register resource usage. The paper then demonstrates a new approach where properties of dynamic reconfiguration can be utilised to perform the tasks of pipeline stage initialisation and flushing. The technique is demonstrated on a real-life application: the demosaic filter in a standard image signal processing pipe used in modern digital cameras, and can be seen to boost the throughput from 16MPixels/s to 51MPixels/s on an example reconfigurable processor.

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The Reconfigurable Instruction Cell Array

Cited by 68 publications

References 12 publications

Reduction of Power Consumption in FPGAs - An Overview

Reduction of Power Consumption in FPGAs - An Overview

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications

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