An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Lamoureux, Julien; Luk, Wayne

doi:10.1109/ahs.2008.71

Cited by 40 publications

(9 citation statements)

References 63 publications

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“…This problem of clock transitions in any part of circuit can be avoided using different clocking strategies. Low -power system design issues [7] Power management required in a system on chip due to following reasons:…”

Section: Background and Motivationmentioning

confidence: 99%

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Kumar

Rattan

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

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The SOCs produced nowadays provide a high level of functionality, serve a wide range of applications, while becoming more efficient and cost effective. The complexity of the SOCs is also reaching its peak level. Around 10 to 12 numbers of analog IPs and digital IPs blocks are incorporated into the single SOC. It also supports multiple voltage domains that often simultaneously a combination of internal and external regulation modes. For modern age embedded systems to operate with high range of power and performance, the system must be power aware but not just consume low power. This paper presents the design detail of embedded RISC processor with dynamic power management capability. In this paper, we implemented a RISC processor with power management that keeps on tracking access to I/O devices while processing and power aware techniques within coding that lower the power consumption of system. Paper describes about the proposed system architecture, synthesis and simulation results analysis of the design. The coding is done with verilog-HDL and these coded designs are synthesized and simulated using Xilinx ISE 12.3 (Xilinx ISim simulator) and power calculation is done using Xilinx Xpower analyzer. Keywords-Dynamic voltage scaling (DVS), Dynamic frequency scheduling (DFS), hardware description language (HDL), Reduced Instruction set computer (RISC), system-on-chip (SoC), field programmable gate array (FPGA).

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Section: Background and Motivationmentioning

confidence: 99%

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Kumar

Rattan

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

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“…clustered architecture) to improve the energy consumption of the FPGA devices [6]. These optimization approaches however, cannot provide adequate solution to reduce the energy requirement for many compute-intensive applications.…”

Section: Introductionmentioning

confidence: 97%

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks

Ghosh

Sauseng

Bhunia

2012

2012 25th International Conference on VLSI Design

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FPGAs have emerged as the preferred prototyping and accelerator platform for diverse application domains such as digital signal processing (DSP), security and multimedia, which often impose real-time performance requirements. Most applications in these domains demand efficient implementation of complex datapaths or functions e.g. transcendental functions, which are spatially mapped in the configurable logic or embedded DSP blocks of a FPGA device. Requirement of elaborate computational resources to realize these operations impose a major barrier to energy efficiency. In this paper, we propose to use embedded memory blocks in FPGA for computing to significantly improve energy efficiency of the applications which are dominated by complex datapaths and/or functions. Complex operations are decomposed or fused into large multiple input/output lookup tables (LUTs); mapped to embedded memory blocks and evaluated through memory access over single or multiple cycles. Different parts of an application are selectively mapped into memory or logic/DSP blocks in a heterogeneous mapping framework to maximize energy efficiency. We explore optimal energy configuration of embedded memory for mapping operations of varying input size and develop a complete mapping flow including decomposition, fusion and packing. Effectiveness of the proposed flow is evaluated for a set of applications using a commercial state-of-the-art FPGA system (Altera Stratix IV). Finally, the proposed framework is extended to drastically trade-off energy versus accuracy at run time for common signal processing applications.

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“…The study presented in [3] explains the system-level and device level design techniques to achieve low power FPGA designs. The paper also describes low power circuit-level and architecture-level design techniques, while emphasizing on power modelling and on low-power computer-aided design (CAD) for FPGAs.…”

Section: Introductionmentioning

confidence: 99%

An optimum ADC output word length selection for low power communication architectures

Manga

Latha

2013

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Low power Very Large Scale Integration (VLSI) design for communication applications is key technology area, driving current mobile communication and wireless networking sectors. The decades of research in Complementary Metal Oxide Semiconductor (CMOS) VLSI technologies could achieve low power design procedures at transistor and circuit level design. To further achieve low power, the researchers are looking at system level design by adopting suitable algorithms and architectures. This paper illustrates one of the power optimization techniques, by reducing the number of ADC output bits, while considering the system level parameters. The dynamic ADC word length optimizer (WLO) is prototyped in VHDL and verified for its functionality in practical signal conditions. The architecture is synthesized for Spartan-6 SX45T FPGA and results demonstrate maximum clock speeds up to 200 MHz, ensuring its compatibility with all types of wideband communication applications with high speed ADCs. Power analysis carried out with Xpower tool show power reduction by 40%. The proposed WLO is simulated and verified for BPSK demodulation, to achieve the theoretical BER limit of 10 -5 at 9.5 dB SNR value.

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An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Abstract: Abstract

Cited by 40 publications

References 63 publications

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks

An optimum ADC output word length selection for low power communication architectures

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