Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Abstract

The SOCs produced nowadays provide a high level of functionality, serve a wide range of applications, while becoming more efficient and cost effective. The complexity of the SOCs is also reaching its peak level. Around 10 to 12 numbers of analog IPs and digital IPs blocks are incorporated into the single SOC. It also supports multiple voltage domains that often simultaneously a combination of internal and external regulation modes. For modern age embedded systems to operate with high range of power and performance, the system must be power aware but not just consume low power. This paper presents the design detail of embedded RISC processor with dynamic power management capability. In this paper, we implemented a RISC processor with power management that keeps on tracking access to I/O devices while processing and power aware techniques within coding that lower the power consumption of system. Paper describes about the proposed system architecture, synthesis and simulation results analysis of the design. The coding is done with verilog-HDL and these coded designs are synthesized and simulated using Xilinx ISE 12.3 (Xilinx ISim simulator) and power calculation is done using Xilinx Xpower analyzer. Keywords-Dynamic voltage scaling (DVS), Dynamic frequency scheduling (DFS), hardware description language (HDL), Reduced Instruction set computer (RISC), system-on-chip (SoC), field programmable gate array (FPGA).

Implementation and Verification of Risc Processor on Fpga Using Chipscope Pro Tool

“…When the alu_in=0001, Rx=000F, Ry=000F, The ALU output is 32-bit 0000_001E. The proposed RISC Processor is compared with similar previous RISC Processor unit [11] concerning resource utilization on the same selected Virtex-6 FPGA. The improvements in slice registers around 82.03%, slice LUT's around 4.55%, LUT-FF pairs are 66.66%, and Input of Input-Outputs is around 55.93% is tabulated in table 2.…”

“…For solving this more power consumption problem a DLX (32-bit architecture). Power consumption and power management work are continues in the next segment, in which Kumar et al [11] have focused on the capability of dynamic power management and to maintain the consumption proposed a low power embedded system. The development of 8-bit RISC processor is possible by the implementation of HDL on the board of FPGA.…”

Hardwired Control Unit Implementation for a 16-Bit Risc Processor Using Verilog

“…Over the last few decades, the RISC (Reduced Instruction Set Computer) processors role in mobile devices, embedded system design, and other applications has significantly improved [1], [2]. RISC processors improves the performance and reduce the power consumption [3].…”