The advanced microprocessors are widely used for most of the complex systems. A silicon chip of fingernail-size may exhibit entire high performance guaranteed processor, higher cache memory and logic needed for interfacing with external devices. Reduced Instruction Set Computing (RISC) is a CPU (Central Processing Unit) design mechanism based on the vision in which exhibits basic instruction set and yields better performance after comparison with microprocessor architecture and it has the capacity to perform the instructions through microprocessor cycles per instruction. In this paper, the Cost-effective and efficient RISC Processor is designed. The RISC Processor design includes Fetching, decoding, Data and instruction memory, and Execution units. The Execution unit contains ALU (Arthematic and Logical Unit) Operations. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device and the physically debugging of the RISC Processor, and ALU Units are verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the RISC Processor is made concerning previous similar architecture with improvements.