The Redistributed Chip Package: A Breakthrough for Advanced Packaging

Keser, Beth; Amrine, C.; Duong, Trung Q.; Fay, Owen; Hayes, Scott; Leal, George; Lytle, W.; Mitchell, Donald E.; Wenzel, R.J.

doi:10.1109/ectc.2007.373811

Cited by 102 publications

(21 citation statements)

References 2 publications

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“…12). Processes such as Freescale' s Redistributed Chip Package (RCP) [37] and Infi neon' s Embedded Wafer Level BGA (eWLB) [38] are two examples that have recently been receiving signifi cant industry attention.…”

Section: Fan Out Packagingmentioning

confidence: 99%

3D and MEMS Packaging

2011

Advancing Microelectronics Magazine

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On the Cover: Pressure distribution over the bottom side of the substrate and its bond pads (as imaged by Topaq Analysis System) IMAPS -International Microelectronics AndPackaging Society 611 2nd Street, NE Washington, DC 20002 Tel: (202) Inside Back Cover Calendar of Events U P C O M I N G E V E N T S F R O M T H E P R E S I D E N T President's MessageMy deepest sympathy and condolence to the Japanese people affected by the recent earthquake and the aftermath that followed. They are in our thoughts and prayers. I have just returned from the International Conference on Electronic Packaging held in Nara, Japan. We have a special bond with the Japanese people because of the common professional interest in microelectronics and electronic packaging industries. Many electronic companies have been directly hit by this disaster.We just had a successful Device Packaging Conference (DPC) in Scottsdale. This conference had leading-edge papers on topics like 3D, wafer-level packaging and fl ipchip technologies. The exhibition had the mix of equipment, materials suppliers and service providers for the technologies relating to conference topics. I have to give kudos to Dr. Phil Garrou and his technical chairs, who did an excellent job of making it happen.The upcoming ATW on High Reliability Microelectronics for Military Applications will address some of these issues. This event will be held on May 17-19, 2011, Holiday Inn Baltimore-BWI International Airport (soon to be the Doubletree BWI -March 2011), Maryland. Greg Caswell and his team have put together an excellent program, another example of great professional volunteerism.As IMAPS President, I am fi nding out that key to a successful event are the general chairs and technical chairs.Our society needs talented and passionate members to organize successful events like DPC. I am requesting of all IMAPS members that if you or someone you know has a passion and talent to hold one of the IMAPS technical events, we need you badly. Please contact me, IMAPS Executive Council Members, or the IMAPS Director or staff to further discuss your ideas on a technical event, which could be a webinar, Advanced Technology Workshop or a conference.So please think what you could achieve if you and a few of your IMAPS friends put your heads together in organizing an event. Volunteer and you will fi nd more rewards than you expected.The focus of this issue is 3D and MEMS Packaging. Today, 3D packaging is the topic of discussion at several packaging conferences including DPC. 3D packaging will enable miniaturization of electronics as never achieved before. Companies are exploring technologies ranging from simple 3D stacking of packages to 3D stacking of ICs using thru-silicon-vias. The infrastructure to fabricate 3D electronics, which was non-existent just a few years ago, is becoming more available. The key to the success of both 3D packaging and MEMS packaging will be low cost and higher functional densities. I hope you enjoy reading the articles on these topics in this issue. Long Beach...

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Section: Fan Out Packagingmentioning

confidence: 99%

3D and MEMS Packaging

2011

Advancing Microelectronics Magazine

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“…And then the build-up layers were fabricated. Freescale proposed a substrate-less embedded chip technology, which is named as Redistributed Chip Package (RCP) [3]. IZM and TUB also introduced a new embedding approach for the 2015 16th International Conference on Electronic Packaging Technology 978-1-4673-7999-1115/$31.00 ©2015 IEEE 3D integration-Chip in Polymer [4] [5].…”

Section: Introductionmentioning

confidence: 99%

Embedding chip into substrates with cavities for hetergeneous integration

Zhang

Shang

Chen

2015

2015 16th International Conference on Electronic Packaging Technology (ICEPT)

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Technologies for the embedding of active and passive components into the multilayer substrate can effectively reduce the circuit length, improve the electrical performance and thermal properties through the designing of thermal path. It allows a large extent miniaturization of products' size and makes high density packaging enabled. In this paper, we embedded the organic interposer with flip-chip into the T-shaped cavity on the core substrate to form an embedded chip package structure. First of all, the thinned chip was flip-mounted on an organic interposer with solder bump, the interposer was fabricated with the circuit pattern as the lead-out module, and meanwhile a T-shaped cavity was machined on an organic core substrate by 355nm laser, which matches the shape of the interposer with chip. Then the interposer was placed in the T-cavity and the core substrate was covered with some prepreg layers. Next embedding chip into substrate was processed by a vacuum lamination machine. At last, laser drilling was used for blind via formation connecting to the pads on the interposer, and via metallization was implemented by vertical PTH and plating process. After the whole processes, thermal cycle test was performed. Results show that the embedded process was demonstrated successfully, and there were no cracks on the die and no voids in the embedded structure.Finally, the steady-state thermal analysis of the embedded substrate was taken to improve the thermal performance and optimum of the embedded substrate.

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“…A lot of activities are running worldwide dealing with wafer level integration. Main drivers are here the Embedded Wafer Level Ball Grid Array (eWLB) by Infineon [2] and the Redistributed Chip Package (RCP) by Freescale [3]. Singulated dies are assembled on an intermediate carrier and encapsulated by compression molding, forming a polymer wafer with embedded silicon dies.…”

Section: Introductionmentioning

confidence: 99%

From wafer level to panel level mold embedding

Braun

Becker

Voges

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-inPolymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8" to 12", for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of today's encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded cmponents and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing µvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production

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The Redistributed Chip Package: A Breakthrough for Advanced Packaging

Cited by 102 publications

References 2 publications

3D and MEMS Packaging

3D and MEMS Packaging

Embedding chip into substrates with cavities for hetergeneous integration

From wafer level to panel level mold embedding

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