The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA

Naylor, Matthew; Runciman, Colin

doi:10.1007/978-3-540-85373-2_8

Cited by 15 publications

(16 citation statements)

References 6 publications

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“…stack size), even though there are successful attempts to create large architectures which could handle this to some degree, like the functional neurons of SyNAPSE architecture by IBM [2]. FPGA-based functional architectures are also attempted, such as the Reduceron [120] and functional design of reconfigurable architectures has been thoroughly explored [29]. Recombination of complete kernels to compose more complex applications by chaining inputs and outputs in a configurable fashion within a processor pipeline (Function Level Processor) has been also attempted with great results, but it does not apply functional programming theory [155].…”

Section: The Von Neumann Bottleneckmentioning

confidence: 99%

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

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Section: The Von Neumann Bottleneckmentioning

confidence: 99%

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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“…This approach (Naylor & Runciman, 2008) is more efficient in some cases, but it cannot be expressed as a core-language transformation.…”

Section: Bounded Template Instantiationmentioning

confidence: 99%

“…Compared to the Reduceron presented in Naylor & Runciman (2008), the implementation described in this paper reduces the number of clock-cycles required to run the benchmark programs by an average factor of 6.4. As the previous implementation clocks at 111 MHz, and the new one at 96 MHz on the same FPGA, the raw speedup factor is 5.5.…”

Section: Comparison With the 2007 Reduceronmentioning

confidence: 99%

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The Reduceron reconfigured and re-evaluated

Naylor

Runciman

2012

J. Funct. Prog.

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A new version of a special-purpose processor for running lazy functional programs is presented. This processor -the Reduceron -exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

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“…SmallCheck is more effective on strict properties and Lazy SmallCheck wins for lazy ones. Of these examples, ListSet is the set implementation using ordered lists (along with the insertion property) given earlier, Countdown is a solver for a popular numbers game (along with a lemma and a refinement theorem) taken from (Hutton 2002), SumPuz is a cryptarithmetic solver (with a soundness property) from (Claessen et al 2002), Circuits is part of a library from the Reduceron (Naylor and Runciman 2008), and Catch is a specification (with a soundness property) for part of the Catch tool (Mitchell and Runciman 2007).…”

Section: Other Examplesmentioning

confidence: 99%

Smallcheck and lazy smallcheck

Runciman

Naylor

Lindblad

2008

Proceedings of the First ACM SIGPLAN Symposium on Haskell

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133

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This paper describes two Haskell libraries for property-based testing. Following the lead of QuickCheck (Claessen and Hughes 2000), these testing libraries SmallCheck and Lazy SmallCheck also use type-based generators to obtain test-sets of finite values for which properties are checked, and report any counter-examples found. But instead of using a sample of randomly generated values they test properties for all values up to some limiting depth, progressively increasing this limit. The paper explains the design and implementation of both libraries and evaluates them in comparison with each other and with QuickCheck.2. the design of Lazy SmallCheck, an alternative which tests properties for partially-defined values, using the results to prune test spaces automatically and parallel conjunction to enable further pruning (currently only first-order properties with universal quantifiers are supported);3. a comparative evaluation of these tools and QuickCheck applied to a range of example properties.

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The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA

Cited by 15 publications

References 6 publications

Modeling, analysis and exploration of layers: A 3D computing architecture

Modeling, analysis and exploration of layers: A 3D computing architecture

The Reduceron reconfigured and re-evaluated

Smallcheck and lazy smallcheck

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