The role of nitridation of nc-Si dots for improving performance of nc-Si nonvolatile memory

Qian, Xinye; Chen, Kunji; Wang, Yuefei; Jiang, Xiaofan; Ma, Zhongyuan; Fang, Zhong-Hui; Xu, Jun; Huang, Xinfan

doi:10.1016/j.jnoncrysol.2012.01.027

Cited by 7 publications

(8 citation statements)

References 7 publications

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“…The recent published literature have shown popular trend in implementing combinations of technical mitigation methods as illustrated in Table 2 to better achieve program/erase characteristics and enhance retention performance in the form of larger memory window (MW). As reported by Qian et al, nitridation was performed on silicon nanocrystals as shown in Figure 10 [47]. This approach yielded larger MW, faster programming speed, and improved retention performance [47].…”

Section: Nanocrystal Memorymentioning

confidence: 96%

“…The research on noncharge based NVM technologies heavily concentrated on the innovation in search of new materials to be applied as new charge storage layer. Even though each of these technical mitigation methods are elucidated separately, but research of combinational mitigation methods is carefully studied for the potential improvements in reliability performance [17][18][19]47]. In Sections 4, 5, and 6, each of these three mature technical solutions was reviewed in detail, that is, top/bottom nitridation of tunnel oxide, nanocrystal quantum dot memory, and PCM.…”

Section: Overview Of Viable Technical Solutionsmentioning

confidence: 99%

“…As reported by Qian et al, nitridation was performed on silicon nanocrystals as shown in Figure 10 [47]. This approach yielded larger MW, faster programming speed, and improved retention performance [47]. Typical quantum dots used in nanocrystal NVM are based on silicon material, but metal nanocrystals, that is, germanium, Au, Gd 2 O 3 , and other refractory metals, are also proposed and researched [40,47,[56][57][58].…”

Section: Nanocrystal Memorymentioning

confidence: 99%

“…Nitrided silicon nanocrystal NVM has shown larger memory window and faster program speed [47] (b) Low random access read latency at ∼50 ns, fast write performance at ∼100 ns, good data retention >10 years, low write and read operating voltage, direct write technology that requires no erase prior to write operation, and good endurance performance at 10 9 cycles [21,[28][29][30] 3 As compared to charge storage NVM, chalcogenide based NVM is immune to charge based radiation effects [35,36] 4 Multilevel cell operation capability [34] Reported endurance failures of PCM are stuck reset of set state (open due to void generated at interface between GST and bottom electrode contact), the stuck set of reset state (small voids spread over the active region that block heat from bottom electrode contact), and tails bit with low resistance from the reset distribution [29] 2 Thermal disturbance effect on V and resistance during reset operation. [21] reported that increase in temperature due to thermal disturbance decreases V drift and reset resistance [27,28] 3 RTN effect found on PCM.…”

Section: Phase Change Memory (Pcm)mentioning

confidence: 99%

“…Nitridation was performed onto silicon nanocrystals that reside in silicon nitride layer to further enhance its reliability performance[47].good endurance/retention performance as compared to SiGe dots with conventional SiO 2 as tunnel dielectric[47]. On the other hand, Wang et al reported the use of Au and Gd 2 O 3 nanocrystals based NVM which exhibited ultrafast program/erase characteristics, disturb-free behavior and multilevel cells capability[58].…”

mentioning

confidence: 99%

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Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM

Lee

Wong

2013

Journal of Nanomaterials

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Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order to meet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run into many critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.

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Section: Nanocrystal Memorymentioning

confidence: 96%

Section: Overview Of Viable Technical Solutionsmentioning

confidence: 99%

Section: Nanocrystal Memorymentioning

confidence: 99%

Section: Phase Change Memory (Pcm)mentioning

confidence: 99%

mentioning

confidence: 99%

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Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM

Lee

Wong

2013

Journal of Nanomaterials

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Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

Chen

et al. 2016

Journal of Applied Physics

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The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

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Microscopic observation of lateral and vertical charge transportation in Si nanocrystals sandwiched by amorphous SiC layers

Lü³

et al. 2018

AIP Advances

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Charge injection and transportation process is a fundamental problem to Si nanocrystals (Si-ncs) based electric and photonic devices. In the manuscript, a single layer of Si-ncs sandwiched by amorphous Si carbide (a-SiC) was prepared by excimer laser annealing of a-SiC/a-Si/a-SiC multilayers, and the charging effect was then characterized by Kelvin probe force microscopy (KPFM) on the microscopic scale. Opposite charges were injected into Si-ncs through the biased tip and formed a core-ring or up-down shaped distribution. The decay characteristics showed that these opposite charges would not only vertically tunnel through the bottom a-SiC layer to substrate but also laterally transport and recombine with each other driven by the attractive Coulomb force. Besides, the charge retention time was also found dependent on the injection biases, which is tentatively ascribed to the charge trapping by the Si-ncs/a-SiC interface states under high bias scanning. The analysis was further supported by conductive atomic force microscopy (CAFM) measurement, in which the current-voltage curves gradually shifted during the repetition test, probably because of bias screening by the trapped charges at these interface states.

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The role of nitridation of nc-Si dots for improving performance of nc-Si nonvolatile memory

Cited by 7 publications

References 7 publications

Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM

Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM

Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

Microscopic observation of lateral and vertical charge transportation in Si nanocrystals sandwiched by amorphous SiC layers

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