The role of plasma analytics in leading‐edge semiconductor technologies

Abstract

Plasma patterning processes play a key role in modern Ultra Large Scale Integration (ULSI) device fabrication. With further scaling of device dimensions, plasma process characteristics become more and more the limiting factor in pattern minimization, not least due to parasitic effects caused by different plasma properties. Such effects are geometrical deviations in the etch profiles, the loss of critical dimensions, the undercut as well as the most critical sidewall damage while etching trenches and vias to fabricate the circuit contact and metallization system. Especially for modern dielectric materials on the base of carbon‐doped silica these drawbacks are much pronounced and worsen performance and power consumption of microelectronic devices. Finally, the charge damage of thin gate oxides during plasma processing results in reduced reliability and functionality of microelectronic devices. The complex interactions between conditions in the plasma bulk and the impacts on the wafer surface are not yet understood completely. With respect to the increasing complexity of modern semiconductor plasma etch equipment, the optimization of patterning processes using the empirical method becomes more and more impossible. This paper overviews typical challenges during plasma patterning processes in 28 nm and 22 nm technology nodes by means of today's Back‐End of Line integration schemes. Different plasma diagnostic methods provide an insight into the physical and chemical conditions of different etch chambers and their influence on process results and damaging behaviour.

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