The role of timing verification in layout synthesis

Benkoski, J.; Strojwas, Andrzej J.

doi:10.1145/127601.122895

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Delay Estimation1

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2003

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Cited by 6 publications

(2 citation statements)

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“…All paths, or a subset of them, are taken into account implicitly in the formulation. Since the delay of a circuit is inherently path-oriented, it is expected I that path-based approaches can obtain better solutions (13,57].…”

mentioning

confidence: 99%

Timing and Area Optimization for VLSI Circuit and Layout

Chuang¹

1994

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mentioning

confidence: 99%

Timing and Area Optimization for VLSI Circuit and Layout

Chuang¹

1994

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“…False path based timing analysis [ 131 uses logic behavior as well as the timing characteristics of the input design to identify false paths. In contract, static timing analysis is concemed with estimating an upper bound on the worst case circuit input-to-output delays by identifying the critical path(s) in that circuit [5].…”

Section: Delay Estimationmentioning

confidence: 99%

A performance driven logic synthesis system using delay estimator

Chen

Tsai

Kurdahi

et al.

Proceedings of 4th Great Lakes Symposium on VLSI

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In this paper, we develop a logic synthesis approach which relies on accurate design evaluation program to estimate the final design attributes such as layout speed. Given a candidate design implementation, an evaluation program will be called upon to provide quick and accurate estimates of the critical path delay. This information will then be used as a feedback to the logic optimization system. Based on this feedback, the system will "re-orient" itself toward a new direction for optimization. Such a scheme represents a more realistic way of generating optimal layout implementations.

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Computer‐Aided Design in Electronics

Domic

2003

Digital Encyclopedia of Applied Physics

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The role of timing verification in layout synthesis

Cited by 6 publications

References 39 publications

Timing and Area Optimization for VLSI Circuit and Layout

Timing and Area Optimization for VLSI Circuit and Layout

A performance driven logic synthesis system using delay estimator

Computer‐Aided Design in Electronics

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