The route to a defect tolerant LUT through artificial evolution

Abstract

Evolutionary techniques may be applied to search for specific structures or functions, as specified in the fitness function. This paper addresses the challenge of finding an appropriate fitness function when searching for generic rather than specific structures which, when combined wiacteristic of defect tolerance on the circuit. Production defects for integrated circuits are expected to increase considerably. To avoid a corresponding drop in yield, improved defect tolerance solutions are needed. In the case of Field Programmable Gate Arrays (FPGAs), the predesigned gate array provides a bridge between production and the application designers. Thus, introduction of defect tolerant techniques to the FPGA itself could provide a defect free gate array to the application designer, despite production defects. The search for defect tolerance presented herein is directed at finding defect tolerant structures for an important building block of FPGAs: Look-Up Tables (LUTs). Two key approaches are presented: (1) applying evolved generic building blocks to a traditional LUT design and (2) evolving the LUT design directly. The results highlight the fact that evolved generic defect tolerant structures can contribute to highly reliable circuit designs at the expense of area usage. Further, they show that applying such a technique, rather than direct evolution, has benefits with respect to evolvability of larger circuits, again at the expense of area usage.

Evolving defect tolerant structures for FPGA architectures

“…As such, the evolutionary experiments require further attention. More detailed information on these experiments may be gleamed from [11].…”

“…X0, X1 and X2 are all dependent on n -the number of transistors in the circuit. As the circuit size increases, X2 increases, reflecting the increased chance of multiple defects -see [11]. Figure 5, illustrates the key elements in the evaluation with respect to equation 3's reliability evaluation.…”

The evolution of standard cell libraries for future technology nodes

“…One potential methodology for achieving this is to use Evolutionary Algorithms (EAs), which have been used in the past to optimise existing CMOS designs for a number of criteria, such as delay [36], area [32], power and yield [42]. EAs have also been used to produce new and unconventional design topologies at both the gate level [27] and device level [40], and also fault-tolerant designs [13,14]. In the majority of cases where EAs have been used, the evolved or optimised designs are not always feasible for fabrication, due to the EA using an insufficient fitness criteria to assess the solutions, which does not take account of a realistic set of factors that affect the design.…”

“…Other researchers have previously manipulated transistor widths whilst evolving defect tolerant topologies for look-up tables, which cope with transistor faults through the use of transistor redundancy [14]. However, the approach described in this paper differs from that of previous researchers by using a multi-objective GA with characterisation-based performance metrics (for example, propagation delay, power), in conjunction with high performance computing resources (HPC) that perform statistical SPICE simulations, in order to ensure that the designs produced have been optimised over a range of criteria and are feasible for fabrication.…”