The S/390 G5 floating point unit supporting hex and binary architectures

Abstract

The rst high performance o ating point unit to support both IBM 360 hexadecimal based o ating point architecture and the IEEE 754 Standard binary oating point architecture is described. The S 390 G5 oating point unit supports the new S 390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This oating point unit is part of the microprocessor chip on the S 390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S 390 G5 represents the current state of the art in CISC processor design. This paper describes the S 390 architecture enhancements, the internal format of the FPU, and the modi cations to the FPU data ow.

Properties of two’s complement floating point notations

“…This notation is in use in well-studied IEEE-754 compliant hardware. Some designs use radix 10 [9], and several of them retain a radix 16 compatibility mode [33]. Yet most systems use radix 2.…”

Architecture and software support in IBM S/390 Parallel Enterprise Servers for IEEE Floating-Point arithmetic

“…• ESA/390 design objectives With the foregoing in mind, the following design objectives were used as a basis for developing the hardware architecture [10] for the ESA/390 floating-point (FP) extensions:…”

“…The following observation reduces the problem to a finite-precision statement: Every binary (or hexadecimal) floating-point number has an exact decimal representation, because all factors of the input base (2) are also factors of the output base (10). Since the range of machine numbers is bounded, there is a longest decimal representation, and this bounds the required precision if decimal arithmetic is used.…”

The IBM eServer z990 floating-point unit

“…The z990 FPU had a variety of predecessors: the 1996 G3 FPU [4], the 1997 G4 FPU [5,6], the 1998 G5 FPU [7,8], the 1999 G6 FPU, and the 2000 z900 FPU [9]. Compared with them, the main z990 FPU goals were to optimize for BFP and have a fast multiply-add execution in order to support the increase in new zSeries workloads, particularly those utilizing Linux**.…”