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The floating-point unit (FPU) of the IBM z990 eServer is the first one in an IBM mainframe with a fused multiply-add dataflow. It also represents the first time that an SRT divide algorithm (named after Sweeney, Robertson, and Tocher, who independently proposed the algorithm) was used in an IBM mainframe. The FPU supports dual architectures: the zSeries hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture. Six floating-point formatsincluding short, long, and extended operands-are supported in hardware. The throughput of this FPU is one multiplyadd operation per cycle. The instructions are executed in five pipeline steps, and there are multiple provisions to avoid stalls in case of data dependencies. It is able to handle denormalized input operands and denormalized results without a stall (except for architectural program exceptions). It has a new extended-precision divide and square-root dataflow. This dataflow uses a radix-4 SRT algorithm (radix-2 for square root) and is able to handle divides and square-root operations in multiple floating-point and fixed-point formats. For fixedpoint divisions, a new mechanism improves the performance by using an algorithm with which the number of divide iterations depends on the effective number of quotient bits.

The rst high performance o ating point unit to support both IBM 360 hexadecimal based o ating point architecture and the IEEE 754 Standard binary oating point architecture is described. The S 390 G5 oating point unit supports the new S 390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This oating point unit is part of the microprocessor chip on the S 390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S 390 G5 represents the current state of the art in CISC processor design. This paper describes the S 390 architecture enhancements, the internal format of the FPU, and the modi cations to the FPU data ow.

The paper presents the design of the Fixed Point Unit (FXU) for the IBM eServer z990 microprocessor (announced in 2Q '03) that runs at 1.2 GHz [2]. The FXU is capable of executing two Register-Memory instructions including arithmetic instructions and a branch instruction in a single cycle. The FXU executes a total of 369 instructions that operate on variable size operands (1 to 256 bytes). The instruction set include decimal arithmetic with multiplies and divides, binary arithmetic, shifts and rotates, loads/stores, branches, long moves, logical operations, convert instructions, and other special instructions. The FXU consists of 64-bit dataflow stack that is custom designed and a control stack that is synthesized. The current FXU is the first superscalar design for the CMOS z-series machines, has a new improved decimal unit, and has for the first time a 16x64 bit binary multiplier.