Proceedings of the 2003 International Symposium on Physical Design 2003
DOI: 10.1145/640000.640014
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The scaling challenge

Abstract: We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of… Show more

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Cited by 28 publications
(1 citation statement)
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“…As VLSI technology moves to the 65 2nm node and be-From practical point of view, slew buffering should be as yond, it has been well documented [1,2] that the number important as timing driven buffering. Unfortunately, there of buffers on a chip is rising dramatically.…”
Section: Introductionmentioning
confidence: 99%
“…As VLSI technology moves to the 65 2nm node and be-From practical point of view, slew buffering should be as yond, it has been well documented [1,2] that the number important as timing driven buffering. Unfortunately, there of buffers on a chip is rising dramatically.…”
Section: Introductionmentioning
confidence: 99%