The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications

Abstract

This paper introduces a novel neural architecture which is capable of similar performance to any of the "classic" neural paradigms while having a very simple and efficient mixed-signal implementation which makes it a valuable candidate for intelligent signal processing in portable multimedia applications. The architecture and its realization circuit are described and the functional capabilities of the novel neural architecture called a simplicial neural cell are demonstrated for both regression and classification problems including nonlinear image filtering.

Synthesis of multiport resistors with piecewise-linear characteristics: a mixed-signal architecture

“…Figure 1 shows a scheme for steps (S1) and (S2), whereas Figure 2 shows a scheme for step (S3). The simpler scheme shown in Figure 3 can be obtained by generalizing the ideas proposed in Reference [12]. The central idea is that the sorting of the z components is obtained sequentially through a voltage ramp r(t) associated with a set of n voltage comparators (the ramp r(t) is deÿned for t ∈ [0; T ], where T is such that r(T ) = V 0 = 1V ).…”

“…For every evaluation point, all non-zero basis functions need to be evaluated, weighted and added, but they are at most n + 1 (that is, linear with respect to the domain dimension), so that the implementation is still remarkably e cient. This principle has been exploited in References [11,12] to derive an electronic implementation for an image processing CNN based on PWL coupled elements. In this paper, we generalize the solution proposed in Reference [11] in the framework of PWL multiport resistor implementations.…”

A fast and compact classifier based on sorting in an iteratively expanded input space

“…Recently, motivated by the need to define a general-purpose, VLSI convenient hardware without too many parameters to be adjusted and with simple and guaranteed learning, the simplicial neuron (or cell) was proposed. 1 This architecture has no multipliers, and the whole knowledge is stored not in distributed synapses (often posing numerous problems for hardware implementation) but in a general purpose RAM memory. The architecture is grounded on the theory of simplicial decomposition, 2,3 and it can be regarded as a form of a kernel-network where the output y of is expressed as…”

“…A simple input expander scheme inspired from the work of Dogaru et al 4 was proposed by Dogaru et al 1 as an effective mean to improve and optimize the classification performance for problems that are highly nonlinear or are characterized by a too small number of inputs. It produces an expanded input vector U, where m i expanded inputs are generated from each input u i with the following straightforward recurrent formula:…”

Towards analog implementations of PWL two-dimensional non-linear functions

“…In particular, for the circuit synthesis we shall refer to the so-called Q-basis and R-basis [2,3]. The Q-basis seems to be more suitable for mixed-signal realizations (an example is given in References [7,8], concerning an electronic implementation for an image processing CNN based on PWL coupling elements).…”