The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Massier, Tobias; Graeb, Helmut; Schlichtmann, Ulf

doi:10.1109/tcad.2008.2006143

Cited by 127 publications

(58 citation statements)

References 35 publications

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“…A minimum yield of 99:9% ( w ¼ 3 in (8)) was required per performance. As for MA and LVA the eight performances in Table 2 and for the LNA the six performances in Table 3 were 12 were considered for all sizing tasks. The yield for each result computed by the new approach was evaluated by a Monte Carlo analysis with 2500 samples at the worst case operating points and is listed in Table 4.…”

Section: Simulation Resultsmentioning

confidence: 99%

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

Pehl¹,

Graeb²

2012

J CIRCUIT SYST COMP

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The design of circuits which are robust against variations in operating and process conditions is crucial in today's IC industry. In the analog design°ow this problem can be tackled during the sizing of a new circuit. However, hardly any methods are available which support the designer to compute such a robust design if discrete parameters should be considered in this design step. Discrete parameters arise predominantly if a layout-friendly sizing should be computed in the sense that, e.g., a manufacturing grid for the transistor lengths and widths is considered or that transistor multipliers are used to allow the layout of a transistor as multi¯nger or common centroid structure without applying rounding operations to the carefully computed sizing. This paper presents a new Branch-and-Bound based approach which allows the automatic computation of a robust design using classical and realistic worst case analysis. The results of the sizing of three circuits show that the new approach is highly e±cient. The robustness of the results computed by the new approach is validated by Monte Carlo analyses.

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Section: Simulation Resultsmentioning

confidence: 99%

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

Pehl¹,

Graeb²

2012

J CIRCUIT SYST COMP

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“…As shown in (Massier et al, 2008), sizing rules of the analog circuits are the constraints that must be satisfied during circuit sizing. They include, for example, geometry constraints (e.g., transistor width, length, area) and electrical constraints (e.g., transistor gate-source voltage V gs , drain-source voltage V ds ).…”

Section: Sizing Rulesmentioning

confidence: 99%

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

Pan¹,

Graeb²

2011

Advances in Analog Circuits

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“…The exact hierarchy is the same as the circuit hierarchy, while the virtual hierarchy consists of hierarchical clusters [17]. Each cluster contains some devices and sub-circuits which are gathered based on device models, sub-circuit functionality [9], [21], and/or other specific constraints [6]. Fig.…”

Section: Hierarchical Placement With Layout Constraintsmentioning

confidence: 99%

Analog layout synthesis - Recent advances in topological approaches

Graeb

Balasa

Castro-López

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

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The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

Cited by 127 publications

References 35 publications

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

Tolerance Design of Analog Circuits Using a Branch-and-Bound Based Approach

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

Analog layout synthesis - Recent advances in topological approaches

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