The SOI MOSFET: from Single Gate to Multigate

Colinge, Jean–Pierre

doi:10.1007/978-0-387-71752-4_1

Cited by 210 publications

(295 citation statements)

References 49 publications

Supporting

Mentioning

270

Contrasting

Unclassified

Order By: Relevance

“…A feasible approach would be, for example, to employ the well-established gate-all-around architeture 10,21 . In order to realize this design, we propose employing a gate last process in order to avoid strain relaxation, where activation of source and drain is performed before patterning, and where low temperature conformal deposition of high-κ gate oxide and metal gate is achieved using atomic layer deposition 22 . Although in the present form, the strained NWs are much larger than what is required to VLSI, strain enhancement is solely dependent on the bridge dimensions such that the structures can be scaled down to the limits that lithography methods provide.…”

Section: Discussionmentioning

confidence: 99%

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

et al. 2012

View full text Add to dashboard Cite

strained si nanowires are among the most promising transistor structures for implementation in very large-scale integration due to of their superior electrostatic control and enhanced transport properties. Realizing even higher strain levels within such nanowires are thus one of the current challenges in microelectronics. Here we achieve 4.5% of elastic strain (7.6 GPa uniaxial tensile stress) in 30 nm wide si nanowires, which considerably exceeds the limit that can be obtained using siGe-based virtual substrates. our approach is based on strain accumulation mechanisms in suspended dumbbell-shaped bridges patterned on strained si-on-insulator, and is compatible with complementary metal oxide semiconductor fabrication. Potentially, this method can be applied to any tensile prestrained layer, provided the layer can be released from the substrate, enabling the fabrication of a variety of strained semiconductors with unique properties for applications in nanoelectronics, photonics and photovoltaics. This method also opens up opportunities for research on strained materials.

show abstract

Section: Discussionmentioning

confidence: 99%

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

et al. 2012

View full text Add to dashboard Cite

show abstract

“…To facilitate calculations of gated devices, we also modified OpenMX to include the gating potential from a cylindrical GAA shell of charge. 45 Sourcedrain voltages are applied by including a potential step in the electrodes and then the charge density is iterated to self consistency. 23 This process of computing DM from H and vice versa iterates until the charge density converges, after which the S-matrix and transmission T(E) are computed for the converged density.…”

Section: Self-consistent Transport Using Negfmentioning

confidence: 99%

Transport properties and electrical device characteristics with the TiMeS computational platform: Application in silicon nanowires

Sharma

Ansari

Feldman

et al. 2013

Journal of Applied Physics

View full text Add to dashboard Cite

Nanoelectronics requires the development of a priori technology evaluation for materials and device design that takes into account quantum physical effects and the explicit chemical nature at the atomic scale. Here, we present a cross-platform quantum transport computation tool. Using first-principles electronic structure, it allows for flexible and efficient calculations of materials transport properties and realistic device simulations to extract current-voltage and transfer characteristics. We apply this computational method to the calculation of the mean free path in silicon nanowires with dopant and surface oxygen impurities. The dependence of transport on basis set is established, with the optimized double zeta polarized basis giving a reasonable compromise between converged results and efficiency. The current-voltage characteristics of ultrascaled (3 nm length) nanowire-based transistors with p-i-p and p-n-p doping profiles are also investigated. It is found that charge self-consistency affects the device characteristics more significantly than the choice of the basis set. These devices yield sourced-drain tunneling currents in the range of 0.5 nA (p-n-p junction) to 2 nA (p-i-p junction), implying that junctioned transistor designs at these length scales would likely fail to keep carriers out of the channel in the off-state. (C) 2013 AIP Publishing LLC

show abstract

“…The short channel-effects can be characterized by the drain-induced barrier lowering (DIBL), sub-threshold (SS) slope and the threshold voltage roll-off [14][15][16]. These effects create technical and scientific challenges, which can be tackled by a careful device design consideration [2,17].…”

Section: Introductionmentioning

confidence: 99%

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

Al-Ameri

Georgiev

Sadi

et al. 2017

Solid-State Electronics

View full text Add to dashboard Cite

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit. Solid-State Electronics, 129, pp. 73-80. (doi:10.1016/j.sse.2016 This is the author's final accepted version.There may be differences between this version and the published version. You are advised to consult the publisher's version if you wish to cite from it.http://eprints.gla.ac.uk/133442/ Deposited on: 04 January 2017 Enlighten -Research publications by members of the University of Glasgow http://eprints.gla.ac.uk 1  Abstract-In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90 o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

show abstract

The SOI MOSFET: from Single Gate to Multigate

Cited by 210 publications

References 49 publications

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

Transport properties and electrical device characteristics with the TiMeS computational platform: Application in silicon nanowires

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

Contact Info

Product

Resources

About