The Specc Methodology

Gajski, Daniel D.; Zhu, Jianwen; Dümer, Rainer; Gerstlauer, Andreas; Zhao, Shuqing

doi:10.1007/978-1-4615-4515-6_4

Cited by 24 publications

(22 citation statements)

References 0 publications

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“…Although there are differences in their details, the ways to describe hardware parts in C and C++ languages share common features. In this paper we target SpecC language 1) when presenting the verification methods as a representative of C based hardware design descriptions. SpecC is an extension over C language in the following ways:…”

Section: Based Design Languagementioning

confidence: 99%

“…It starts with a rather algorithmic description of the target design and tries to refine it into a high-level synthesizable model. Here it is assumed that algorithmic design descriptions written in C/C++ or their extended counterparts such as SpecC 1) and SystemC 2) language are given as specifications. In some cases these algorithmic descriptions can be found in the definitions of standards for image compression/decompression techniques, communication protocols and encryption methods.…”

Section: Introductionmentioning

confidence: 99%

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Trends in Formal Verification Techniques for C-based Hardware Designs

Fujita

2009

IPSJ Transactions on System LSI Design Methodology

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Three formal verification approaches targeting C language based hardware designs, which are the central verification technologies for C-based hardware design flows, are presented. First approach is to statically analyze C design descriptions to see if there is any inconsistency/inadequate usages, such as array overbounds accesses, uses of values of variables before initialization, deadlocks, and others. It is based on local analysis of the descriptions and hence applicable to large design descriptions. The key issue for this approach is how to reason about various dependencies among statements as precisely as possible with as short time as possible. Second approach is to model check C design descriptions. Since simple model checking does not work well for large descriptions, automatic abstractions or reductions of descriptions and their refinements are integrated with model checking methods such that reasonably large designs can be processed. By concentrating on particular types of properties, there can be large reductions of design sizes, and as a result, real life designs could be model checked. The last approach is to check equivalence between two C design descriptions. It is based on symbolic simulations of design descriptions. Since there can be large numbers of execution paths in large design descriptions, various techniques to reduce the numbers of execution paths to be examined are incorporated. All of the presented methods use dependence analysis on data, control, and others as their basic analysis techniques. System dependence graph for programming languages are extended to deal with C based hardware designs that have structural hierarchy as well. With those techniques, reasonably large design descriptions can be checked.

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Section: Based Design Languagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Trends in Formal Verification Techniques for C-based Hardware Designs

Fujita

2009

IPSJ Transactions on System LSI Design Methodology

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“…C or C++ based design languages such as SpecC [1] or SystemC [2] are uniformly used to describe both hardware and software parts.…”

Section: Introductionmentioning

confidence: 99%

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath

Nishihara

Matsumoto

Fujita

2009

IEICE Trans. Inf. & Syst.

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SUMMARYEquivalence checking is one of the most important issues in VLSI design to guarantee that bugs do not enter designs during optimization steps or synthesis steps. In this paper, we propose a new word-level equivalence checking method between two models before and after highlevel synthesis or behavioral optimization. Our method converts two given designs into RTL models which have same datapaths so that behaviors by identical control signals become the same in the two designs. Also, functional units become common to the two designs. Then word-level equivalence checking techniques can be applied in bit-level accuracy. In addition, we propose a rule-based equivalence checking method which can verify designs which have complicated control structures faster than existing symbolic simulation based methods. Experimental results with realistic examples show that our method can verify such designs in practical periods.

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“…//Lowest data channel (lower communication method) interface I_xbus_EB_0 { void xbus_write_word_burst(unsigned int data [4]); void xbus_read_word_burst(unsigned int data [4]); }; channel xbus_EB_0(void) implements I_xbus_EB_0 { //definition of bus protocol note protocol = "Gen_svhhtLIDCT10_HWEB"; unsigned int buff_word_burst [4]; // buffer bool status_word_burst = false; // status event ready_word_burst, done_word_burst; // event for sync void xbus_write_word_burst(unsigned int data [4] In this experiment, we only designed the MPEG-4 decoder and used a simple model (reduced function model) of MPEG-4 algorithms. All the function of this example was specified using functional VCores.…”

Section: Architecture Design Experimentsmentioning

confidence: 99%

“…Functional VCores, software VCores and hardware VCores were designed using SpecC language [4] beforehand. Firstly, an initial architecture of the W -Com, which has 32-bit MIPS-Lite processor (almost equivalent to the MIPS R3000 microprocessor [6]) and W -Com 32-bit read and write buses (almost equivalent to the EC bus [5]) was configured using the W -Com architecture template.…”

Section: Architecture Design Experimentsmentioning

confidence: 99%

Design methodology for SoC architectures based on reusable virtual cores

Muraoka¹,

Nishi²,

Morizawa³

et al.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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The design reuse methodology, which has been developed at the VCDS Project, is a SoC design methodology to reduce the SoC design time using high level design intellectual properties named as Virtual Cores (VCores). In this paper, we propose the VCore based design methodology to synthesize the SoC architecture from the system level specification. This synthesis methodology generates an initial architecture that consists of a CPU, buses, I/Os peripherals, and RTOS (Real Time Operating System), and makes tradeoffs between hardware and software on assigned software VCores and hardware VCores models to the architecture. The results of an architecture level design experiment using the proposed methodology shows that the partial automation of the communication refinement process, allied with design reuse, accelerates the architecture synthesis, thus reducing the design time required to design an architecture.

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The Specc Methodology

Cited by 24 publications

References 0 publications

Trends in Formal Verification Techniques for C-based Hardware Designs

Trends in Formal Verification Techniques for C-based Hardware Designs

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath

Design methodology for SoC architectures based on reusable virtual cores

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