The Sprite Input Language-an intermediate format for high level synthesis

Krol, Th.; Meerbergen, J. van; Niessen, C.; Smits, W. J. M.; Huisken, Jos

doi:10.1109/edac.1992.205920

Cited by 19 publications

(4 citation statements)

References 11 publications

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“…The termination condition of unbounded loop constructs is typically influenced by the code in the body of the loop. Examples of unbounded recursion constructs are while-loops, as in the case of C and VHDL, or graph-recursion constructs, as in the case of the signal flow graph language SIL [Krol et al 1992] (SIL is used as input language to the high-level synthesis system PHIDEO [van Meerbergen et al 1995]). The problem with unbounded recursion constructs is that they do not necessarily lead to terminating computations (which is of course precisely the reason why these languages are able to express functions that are not completely defined on their entire domain).…”

Section: Incompleteness In Common Design Languagesmentioning

confidence: 99%

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On the fundamental limitations of transformational design

Voeten

2001

ACM Trans. Des. Autom. Electron. Syst.

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The completeness of a collection of design transformations is an important aspect in transformational design. Completeness guarantees that any correct design can in principle be explored using the transformation system. In the field of transformational design the problem of incompleteness is not well understood and it is often believed that complete transformation systems can be constructed. In this article, we show, using a formal framework based on the theory of computation, that this is not the case if the transformation system is based on an expressive general-purpose design language such as VHDL. Only when restrictions are imposed on the design language and correctness relation, a transformation system can be made complete in theory, but this is expected to result in serious practical problems. It is shown that the incompleteness problem in transformational design is closely related to the syntactic variance problem in high-level synthesis and that this latter problem is not solvable in general either.

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Section: Incompleteness In Common Design Languagesmentioning

confidence: 99%

“…In Middelhoek [1997], for instance, it is questioned whether a complete transformation system for the signal flow graph language SIL [Krol et al 1992] exists. In Vemuri [1990], a proof technique for completeness of a set of register level design transformations is given.…”

Section: Introductionmentioning

confidence: 99%

On the fundamental limitations of transformational design

Voeten

2001

ACM Trans. Des. Autom. Electron. Syst.

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“…They are, for instance, used in the Cathedral [DeMan et al 1986], Piramid [Woudsma et al 1990], and as DFL in the commercial DSP Station tools. The proven applicability of CDFG languages to digital design and the need for compositional formal semantics made us choose the CDFG-like language SIL [Kloosterhuis et al 1992;Krol et al 1992], which integrates both control and data flow into a single graph and has formal semantics [Huijs and Krol 1994]. SIL has been developed cooperatively by Philips Research, IMEC, and the University of Twente as part of the EC-funded ESPRIT/SPRITE project.…”

Section: Design Representationmentioning

confidence: 99%

From VHDL to efficient and first-time-right designs

Middelhoek

Sunitha

1996

ACM Trans. Des. Autom. Electron. Syst.

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In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. We do this while taking into account the complete life cycle of a design from early prototype to full custom implementation. Besides time-to-market, both flexibility with respect to target architecture and efficiency issues are addressed by the methodology. The utilization of user-selected behaviorpreserving transformation steps ensures first-time-right designs while exploiting the experience, flexibility, and creativity of the designer.To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent of a specific behavioral model or graph size has been developed.As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. Both a video signal processor-based prototype implementation as well as a very efficient full custom implementation are developed starting from a single high-level behavioral specification of the algorithm in VHDL. Results are compared with those previously obtained using different tools and methodologies.

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“…The data flow graph format is similar to the SIL (Synthesis Intermediate Language) intermediate format used in the European Esprit project [32]. The control flow graph format is mostly based on DDS [33] and supports the typical constructs used in procedural languages such as C and VHDL processes (e.g.…”

Section: Codesyn: Retargetable Code Generationmentioning

confidence: 99%

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

Paulin¹,

Liem²,

May

et al. 1995

Journal of VLSI Signal Processing

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Abstract. This paper describes the trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR) 1 and the tools needed to address them. The paper is in three parts: First, we present the results of a three month survey of DSP design practices at BNR. We briefly describe the characteristics of the designs, as well as the DSP design tools used. However, the emphasis is on the main bottlenecks in the design process, and the tools required to address them in the future. Then, we present a proposal for a next generation DSP design environment for telecommunication applications, based on the survey results. Particular emphasis will be given to code generation, system-level simulation, and behavioral synthesis, the three most requested design tools. Finally, we provide a description of FlexWare, an embedded software development system which is being developed internally. This system addresses one important aspect of this next generation environment, namely design tools for application-specific instruction-set processors (ASIP). FlexWare is composed of two main components: CodeSyn, a retargetable microcode synthesis system; and Insulin, a VHDL-based instruction set simulation system.

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The Sprite Input Language-an intermediate format for high level synthesis

Cited by 19 publications

References 11 publications

On the fundamental limitations of transformational design

On the fundamental limitations of transformational design

From VHDL to efficient and first-time-right designs

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

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