The Stanford Hydra CMP

Hammond, Lance; Hubbert, B.A.; Siu, M. Stewart; Prabhu, Manohar K.; Chen, M.; Olukolun, K.

doi:10.1109/40.848474

Cited by 263 publications

(144 citation statements)

References 12 publications

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“…In particular, we add a backup buffer to each L1 cache. A line is moved to the backup buffer when it is in a backup state, it needs to be replaced and there is enough room in the backup buffer 4 . The backup buffer acts as a small victim cache, except that only lines in backup states are moved to it.…”

Section: Avoiding Data Lossmentioning

confidence: 99%

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A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

Fernández-Pascual

Garcia

Acacio

et al. 2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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Section: Avoiding Data Lossmentioning

confidence: 99%

“…Chip Multiprocessors (CMPs) [4,3] are currently accepted as the best way to take advantage of the increasing number of transistors available in a single chip, since they provide better performance without excessive power consumption exploiting thread-level parallelism.…”

Section: Introductionmentioning

confidence: 99%

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

Fernández-Pascual

Garcia

Acacio

et al. 2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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show abstract

“…When the granularity of parallelism is too small or there is limited parallelism in the program, the software overhead overwhelms any potential performance benefits from speculative thread parallelism. Empirical results [12] have shown that communication and synchronization operations can take ∼100 cycles for most speculation operations. Thus, in order to amortize these overheads, the size of threads should be in the range of ∼1000 instructions.…”

Section: Speculationmentioning

confidence: 99%

Value Prediction and Speculative Execution on GPU

Liu

Eisenbeis

Gaudiot

2010

Int J Parallel Prog

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GPUs and CPUs have fundamentally different architectures. It is conventional wisdom that GPUs can accelerate only those applications that exhibit very high parallelism, especially vector parallelism such as image processing. In this paper, we explore the possibility of using GPUs for value prediction and speculative execution: we implement software value prediction techniques to accelerate programs with limited parallelism, and software speculation techniques to accelerate programs that contain runtime parallelism, which are hard to parallelize statically. Our experiment results show that due to the relatively high overhead, mapping software value prediction techniques on existing GPUs may not bring any immediate performance gain. On the other hand, although software speculation techniques introduce some overhead as well, mapping these techniques to existing GPUs can already bring some performance gain over CPU. Based on these observations, we explore the hardware implementation of speculative execution operations on GPU architectures to reduce the software performance overheads. The results indicate that the hardware extensions result in almost tenfold reduction of the control divergent sequential operations with only moderate hardware (5-8%) and power consumption (1-5%) overheads.

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“…Most SpMT system relies on compiler to generate parallel threads [4,5,10,11]. We develop Prophet compiler to divided the sequential program into parallel threads despite uncertainty whether these thread are actually independent or not.…”

Section: Introductionmentioning

confidence: 99%

Prophet: A Speculative Multi-threading Execution Model with Architectural Support Based on CMP

Dong

Zhao

Wei

et al. 2009

2009 International Conference on Scalable Computing and Communications; Eighth International Conference on Embedded Computing

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Abstract--Speculative Multithreading (SpMT) has been proposed as a perspective method to exploit Chip Multiprocessors (CMP) hardware's potential. It is a thread level speculation (TLS) model mainly depending on software and hardware co-design. This paper researches speculative thread-level parallelism of general-purpose programs and a speculative multi-threading execution model called Prophet is presented. The architectural support for Prophet execution model is designed based on CMP. In Prophet the inter-thread data dependences are predicted by pre-computation slice (p-slice) to reduce RAW violation. Prophet Multi-versioning Cache system along with thread state control mechanism in architectural support are utilized for buffering the speculative data, and a snooping bus based cache coherence protocol is used to detect data dependence violation. The simulation-based evaluation shows that the Prophet system could achieve significant speedup for general-purpose programs.

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The Stanford Hydra CMP

Cited by 263 publications

References 12 publications

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

Value Prediction and Speculative Execution on GPU

Prophet: A Speculative Multi-threading Execution Model with Architectural Support Based on CMP

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