The status of high-speed trigger multiplexer module with aurora protocol implemented on Arria II FPGA for the Belle II Cylindrical Drift Chamber detector

Teng, Yao; Wang, C.-H.; Liu, S.-M.; Shiu, J. G.; Lai, Yu-Ting; Lin, Chun-Ju

doi:10.1109/nssmic.2013.6829748

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“…It consists of several systems, and one of the major systems is the level one central drift chamber (CDC) trigger. The level one CDC trigger algorithms are implemented on merger boards [23] and third generation universal trigger boards (UT3), which are 6U VME [24] boards with optical cables. The UT3 board was developed by the high energy accelerator research organization (KEK) for the Belle II level one trigger.…”

Section: Implementation Examplesmentioning

confidence: 99%

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

Kim

Won

2018

Nuclear Instruments and Methods in Physics Research Section A:

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Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

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Section: Implementation Examplesmentioning

confidence: 99%