The structure of the limit cycles in sigma delta modulation

Friedman, V.

doi:10.1109/26.3777

Cited by 101 publications

(50 citation statements)

References 9 publications

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“…Thus, there is a set of equalities, (5), and a set of inequalities, (7), that need to be fullfilled in order to have a valid LC. Substitution of (3) in (7) gives (8) which is equivalent to (9) by defining . Hence, one needs to simultaneously solve (5) and (9) in order to have a valid LC; in the next section more specific solutions will be derived for various SDM topologies.…”

Section: B General Formulation Of Lc Conditionsmentioning

confidence: 99%

“…Substitution of (3) in (7) gives (8) which is equivalent to (9) by defining . Hence, one needs to simultaneously solve (5) and (9) in order to have a valid LC; in the next section more specific solutions will be derived for various SDM topologies.…”

Section: B General Formulation Of Lc Conditionsmentioning

confidence: 99%

“…There is only one solution to (5). If this solution also complies with all inequalities (9), it results in a LC. Because the null space is zero, any change of the integrator states would result in a break-up of the LC.…”

Section: B No DC Polesmentioning

confidence: 99%

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Description of limit cycles in sigma-delta modulators

Reefman

Reiss

Janssen

et al. 2005

IEEE Trans. Circuits Syst. I

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Abstract-A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma-delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is on dc inputs, since this represents the most relevant practical condition. An outcome of the analysis is that, in general, for an th-order SDM, at least 1 initial conditions need to be fixed in order to have LC behavior. Expressions for the minimum disturbance of the input or initial conditions that is needed to break up a LC are also presented. Special focus is given to the case where the disturbance takes the form of "dithering the quantizer", and it is shown that this form of dither is a suboptimal approach to remove LCs. The stability of LCs is determined, and it is demonstrated that a resonator section, as often employed to increase the dynamic range of an SDM, has an adverse effect on LC behavior in that it stabilizes LCs. Furthermore, the experimental observation that high order SDMs are less susceptible to LCs is underpinned. Finally, some examples are provided which illustrate the theoretical results.

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Section: B General Formulation Of Lc Conditionsmentioning

confidence: 99%

Section: B General Formulation Of Lc Conditionsmentioning

confidence: 99%

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Description of limit cycles in sigma-delta modulators

Reefman

Reiss

Janssen

et al. 2005

IEEE Trans. Circuits Syst. I

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“…The bit streams that correspond to admissible periodic orbits of this system can be found by application of an algorithm due to Euclid (Friedman, 1988), and have the property that the ones and zeros (representing levels of 1 and -1) that make up the orbit are distributed as evenly as possible (Gray, 1987). This concept of approximating a value by alternating between two (or more) possibilities, and doing so in a way that has certain desirable and studied in (Feely and Chua, 1991).…”

Section: Application To Sigma-delta Modulation and Related Electronicmentioning

confidence: 99%

Discontinuous piecewise‐linear discrete‐time dynamics – maps with gaps in electronic systems

Feely

2011

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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PurposeMany important electronic systems are modelled by discrete-time equations with nonlinearities that are discontinuous and piecewise-linear, often arising as a result of quantization.Approximations based on linearization -the standard engineering response to nonlinearity -are often quite unhelpful in these systems, because of the form of the nonlinearity. Certain methods and results have been developed over a number of years for the analysis of discontinuous piecewise-linear discrete-time dynamics. The aim of this tutorial paper is to review that body of knowledge, and to show how it can be applied to representative electronic systems. ApproachThe paper uses an important electronic circuit -the sigma-delta modulator -as a central example, and considers the dynamical behaviour exhibited by this circuit and related circuits. FindingsThe circuits under investigation exhibit complex forms of behaviour that can be explained by the application of methods of nonlinear discrete-time dynamics. ValueThis paper is intended to provide a brief introduction to the body of research that exists into the behaviour of nonlinear discrete-time circuits and systems with discontinuous piecewise-linear nonlinearities.3

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“…These complications are worsened in the context of fractional-synthesis, because the modulator is implemented in the digital domain, and due to the finite-word-length of the arithmetic, the input as well as all the internal states are represented by rational numbers. It is commonly observed that simple rational dc inputs to the modulator produce purely limit cycle oscillations and tones, and hence, no noise shaping is present at all [15], [16].…”

mentioning

confidence: 99%

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

Kozak

Kale

2004

IEEE Trans. Circuits Syst. I

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Abstract-In this paper, rigorous analyses are presented for higher order multistage noise shaping (MASH) Delta-Sigma (16) modulators, which are built out of cascaded first-order stages, with rational dc inputs and nonzero initial conditions. Asymptotic statistics such as the mean, average power, and autocorrelation of the binary quantizer error are formulated using a nonlinear difference equation approach. An important topic of interest considered here is the fractional-phase-locked-loop frequency synthesis applications, where the input to the modulator has to be a rational constant. It has been mathematically shown that, regardless of the initial conditions, first-order and second-order MASH 16 modulators with rational dc inputs cannot sufficiently randomize the quantization error samples, and, therefore, are not suitable for fractionalsynthesis applications. An irrational initial condition imposed on the first accumulator of a third or higher order MASH modulator, on the other hand, annihilates the tones throughout the whole output spectrum, and provides a very smooth noise shaping. Simulation results are provided to support the theoretically derived results. Implementation issues of the irrational initial condition in the digital domain are also discussed and investigated together with the effect of finite accumulator size on the noise-shaping quality factor.

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The structure of the limit cycles in sigma delta modulation

Cited by 101 publications

References 9 publications

Description of limit cycles in sigma-delta modulators

Description of limit cycles in sigma-delta modulators

Discontinuous piecewise‐linear discrete‐time dynamics – maps with gaps in electronic systems

Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis

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The structure of the limit cycles in sigma delta modulation

Cited by 101 publications

References 9 publications

Description of limit cycles in sigma-delta modulators

Description of limit cycles in sigma-delta modulators

Discontinuous piecewise‐linear discrete‐time dynamics – maps with gaps in electronic systems

Rigorous Analysis of Delta–Sigma Modulators for Fractional-&lt;tex&gt;$N$&lt;/tex&gt;PLL Frequency Synthesis

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Rigorous Analysis of Delta–Sigma Modulators for Fractional-<tex>$N$</tex>PLL Frequency Synthesis