The supersmall soft processor

Robinson, James T.; Vafaee, Sam; Scobbie, Jonathan; Ritche, Michael; Rose, Jonathan

doi:10.1109/spl.2010.5483016

Cited by 21 publications

(8 citation statements)

References 9 publications

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“…The purpose of Supersmall [3], a small soft processor that supports a subset of the MIPS-I ISA, is to implement a 32-bit microprocessor within a limited and small hardware amount of FPGAs. Figure 1 shows Supersmall's architecture.…”

Section: Supersmall Soft Processormentioning

confidence: 99%

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Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

Takamaeda-Yamazaki

Nakatsuka

Tanaka

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYSoft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these deviceindependent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach. key words: soft processor, processor architecture, FPGA

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Section: Supersmall Soft Processormentioning

confidence: 99%

“…Ultrasmall is based on Supersmall [3], a previous tiny soft processor of the MIPS ISA with a 1-bit serial ALU. Supersmall has a multi-cycle structure, not a pipelined structure, for low resource utilization.…”

Section: Introductionmentioning

confidence: 99%

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

Takamaeda-Yamazaki

Nakatsuka

Tanaka

et al. 2015

IEICE Trans. Inf. & Syst.

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“…A small design of a RISC MCU with a invariant instruction execution time is given by the Open uRISC [16]. The 'supersmall' soft-core processor is focused on applications with very low speed requirements [17]. It is designed to squeeze the last little bit out of the processor's design.…”

Section: Related Workmentioning

confidence: 99%

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

Stecklina

Methfessel

2014

2014 17th Euromicro Conference on Digital System Design

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In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is adequate for control tasks, which require decision making that could not easily be implemented in an application specific integrated circuit (ASIC) and in which an extensive mathematical processing is not required. Especially in the area of embedded control tasks with real-time requirements an architecture using singlecycle instructions is key. We will illustrate an application of our TinyVLIW8 by presenting an design of a secure wake-up receiver for low power wireless sensor nodes. To the best of our knowledge, the presented soft-core processor is the smallest VLIW design with an average instruction execution time of one clock cycle only. The core consumes less than 6 % of the logic cells of the smallest Altera Cyclone IV FPGA and can be used in a system-on-chip design as well.

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“…This can be accomplished in a multitude of ways, dependent on the processor's memory configuration. In general, processor cores are classified as either hard or soft [18]. The designation of a core being either hard or soft refers to its flexibility or ability to be configured.…”

Section: Sopc Design Flowmentioning

confidence: 99%

Design of the Nios II System for the Playing of Wave Files on an Altera DE2 Board

Moslehpour¹,

Jenab²,

Weinsier³

et al. 2013

IJET

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Abstract-The motivation behind this study is the impact made on today's social media by music players, which include features like portability, size and equalizer functionality for the best possible sound output quality. The objective of this study was to develop a system that reads the wave files present on the Secure Data (SD) card, adjust the equalizer settings incorporated on it, and play them on the speaker with the best possible quality sound output. This was done with the help of the SD card slot provided on the DE2 board, and its implementation on the board using Altera's SoPC (System-ona-Programmable-Chip) Builder in the Altera Quartus 9.1 environment. Nios II is a 32-bit soft-core embedded processor architecture designed specifically for the Altera family of FPGAs. Programming of the Nios II processor is done using the Nios II 9.1 IDE tool. An extension of this work could include incorporation of video-along with the audio on the DE2 board since there is a VGA slot included on the board features and the movement of the wave files on the SD card with the help of the keys present on the DE2 board.Index Terms-Embedded processor, Nios II embedded design, SoPC builder, and system on a programmable chip builder.

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The supersmall soft processor

Cited by 21 publications

References 9 publications

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

Design of the Nios II System for the Playing of Wave Files on an Altera DE2 Board

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