Soft processors have become an increasingly common component of systems that use Field-Programmable Gate Arrays (FPGAs), and are used to implement a wide variety of control and data processing functionality. Often, some additional functionality needs to be added to a system when there is very little space left on the physical device. This functionality may not be performance critical, and so could be implemented on a slow soft processor. For this reason it may be useful to have a processor that is as small as possible yet similar to other commonly-used processors. This paper describes the design, implementation and release of a 32-bit soft processor based on the MIPS-I instruction set and optimized for minimal use of FPGA resources. The 'supersmall' soft processor is as much as 2.2 times smaller than Altera's Nios II/e (the smallest of their 3 processors) yet only a factor of 10 times slower.