The survey on ARM processors for HPC

Yokoyama, Daniel; Schulze, Bruno; Borges, Fábio; Evoy, Giacomo V. Mc

doi:10.1007/s11227-019-02911-9

Cited by 29 publications

(19 citation statements)

References 78 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…ISAcc [115], [116] provides an additional set of instructions for RISC and CISC architectures. These additional instructions enable a single CPU instruction to performs a specific part of the computation that is needed by an application in a single CPU execution cycle.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…Content may change prior to final publication. [116] AES-NI [117], [118] DRNG [119] AVX [120]- [123] SSE [124], [125] CPU Identi. [126] VM Ext.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…[127]- [129] Deep Learning Boost [32] CPU Pinning [130], [131] Cache Coherency Cache Hierarchy [132] DDIO [133] CPU Clock [134] Base Frequency [135] Turbo Frequency [136] Over [143] ARM Arch. in HPC RISC Design [116] Hyper-Scale Comp., Neoverse N1 ® [144], [145] ?…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

See 2 more Smart Citations

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

View full text Add to dashboard Cite

In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

show abstract

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…Content may change prior to final publication. [116] AES-NI [117], [118] DRNG [119] AVX [120]- [123] SSE [124], [125] CPU Identi. [126] VM Ext.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

See 1 more Smart Citation

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

View full text Add to dashboard Cite

show abstract

“…More recently, the low levels of energy consumption of Arm-based processors have also attracted the interest of HPC communities [6]. In this direction, several research works and projects [7,8] have investigated the use of Arm mobile CPUs as building blocks for new generations of energy-efficient systems [9], and a comprehensive software ecosystem has been developed to easily deploy and operate HPC Arm-based clusters [10]. These projects have also highlighted the lack, in these Arm processors, of some important features for HPC, such as: high bandwidth data paths to connect together multiple processors, capability to sustain peak computing performances for a long amount of time, and high number of cores to provide an high peak computing throughput.…”

Section: The Appearance Of Arm In Hpcmentioning

confidence: 99%

ThunderX2 Performance and Energy-Efficiency for HPC Workloads

et al. 2020

View full text Add to dashboard Cite

In the last years, the energy efficiency of HPC systems is increasingly becoming of paramount importance for environmental, technical, and economical reasons. Several projects have investigated the use of different processors and accelerators in the quest of building systems able to achieve high energy efficiency levels for data centers and HPC installations. In this context, Arm CPU architecture has received a lot of attention given its wide use in low-power and energy-limited applications, but server grade processors have appeared on the market just recently. In this study, we targeted the Marvell ThunderX2, one of the latest Arm-based processors developed to fit the requirements of high performance computing applications. Our interest is mainly focused on the assessment in the context of large HPC installations, and thus we evaluated both computing performance and energy efficiency, using the ERT benchmark and two HPC production ready applications. We finally compared the results with other processors commonly used in large parallel systems and highlight the characteristics of applications which could benefit from the ThunderX2 architecture, in terms of both computing performance and energy efficiency. Pursuing this aim, we also describe how ERT has been modified and optimized for ThunderX2, and how to monitor power drain while running applications on this processor.

show abstract

“…Nevertheless, it is important to highlight that IoT may benefit from the existing literature on the usage of low-power arm processors for high-performance computing (HPC) where energy efficiency has become a key challenge to address Exascale needs [31], highlighting the importance of the relationship between performance and energy consumption in the development of HPC systems. A survey which includes a list of articles mainly focused on the use of Arm processors to reduce the energy consumption of HPC infrastructure can be found in [32]. For instance, the role played by hardware factors and by some software aspects in the energy-performance landscape of real-life HPC applications is analyzed in detail in [33], and a combination of both architecture and software improvements to optimize performance and energy consumption on arm-based platforms by using dynamic voltage and frequency scaling (DVFS) techniques, multithreading and vectorization is proposed in [34].…”

Section: Related Workmentioning

confidence: 99%

Analysis of Energy Consumption and Optimization Techniques for Writing Energy-Efficient Code

Corral-García¹,

Lemus-Prieto²,

Pérez-Toledano

2019

Electronics

View full text Add to dashboard Cite

The unprecedented growth of connected devices, together with the remarkable convergence of a wide variety of technologies, have led to an exponential increase in the services that the internet of things (IoT) can offer, all aimed at improving quality of life. Consequently, in order to meet the numerous challenges this produces, the IoT has become a major subject of research. One of these challenges is the reduction of energy consumption given the significant limitations of some devices. In addition, although the search for energy efficiency was initially focused on hardware, it has become a concern for software developers too. In fact, it has become an intense area of research with the principal objective of analyzing and optimizing the energy consumption of software systems. This research analyzes the energy saving that can be achieved when using a broad set of techniques for writing energy-efficient code for Raspberry Pi devices. It also demonstrates that programmers can save more energy if they apply the proposed techniques manually than when relying on other automatic optimization options offered by the GNU compiler collection (GCC). Thus, it is important that programmers are aware of the significant impact these techniques can have on an application’s energy consumption.

show abstract

The survey on ARM processors for HPC

Cited by 29 publications

References 78 publications

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

ThunderX2 Performance and Energy-Efficiency for HPC Workloads

Analysis of Energy Consumption and Optimization Techniques for Writing Energy-Efficient Code

Contact Info

Product

Resources

About