ThunderX2 Performance and Energy-Efficiency for HPC Workloads

Calore, Enrico; Gabbana, Alessandro; Schifano, Sebastiano Fabio; Tripiccione, R.

doi:10.3390/computation8010020

Cited by 15 publications

(7 citation statements)

References 34 publications

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“…Certain errors could exist due to the accuracy of on-chip sensor for instantaneous readings reported in [57]. However, as our aim is to analyze only calculation energy cost, it is the only way for collecting on-chip component energy data [41], [58] and reported to be fairly accurate by NVIDIA (+-5% error rate [59]) and authors in [60], [61]. As the problem does not influence theoretical TOs/FLOPs, we will not discuss the accuracy of hardware energy monitoring.…”

Section: Methods Verificationmentioning

confidence: 99%

A Transistor Operations Model for Deep Learning Energy Consumption Scaling Law

Tsourdos

Guo

2024

IEEE Trans. Artif. Intell.

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Deep Neural Networks (DNN) has transformed the automation of a wide range of industries and finds increasing ubiquity in society. The high complexity of DNN models and its widespread adoption has led to global energy consumption doubling every 3-4 months. Current energy consumption measures largely monitor system wide consumption or make linear assumptions of DNN models. The former approach captures other unrelated energy consumption anomalies, whilst the latter does not accurately reflect nonlinear computations. In this paper, we are the first to develop a bottom-up Transistor Operations (TOs) approach to expose the role of non-linear activation functions and neural network structure. As there will be inevitable energy measurement errors at the core level, we statistically model the energy scaling laws as opposed to absolute consumption values. We offer models for both feedforward DNNs and convolution neural networks (CNNs) on a variety of data sets and hardware configurations -achieving a 93.6% -99.5% precision. This outperforms existing FLOPs-based methods and our TOs method can be further extended to other DNN models.Impact Statement-Deep learning is one of the fastest growth areas for computational resources (300,000x from 2012 to 2018, doubling every 3-4 months). Data centres are predicted to dominate over 20% of global energy consumption by 2030. Our proposed TOs model provides developers with a theoretical model to expose the important role of both (1) nonlinear activation functions and (2) DNN model structure in its energy consumption. This enables developers to trade-off between model performance and sustainability with 93.6% -99.5% precision. Due to the consideration of both linear and non-linear operation in TOs, it can to some extent replace FLOPs/MACs count as a more accurate metric of DNN model complexity.

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Section: Methods Verificationmentioning

confidence: 99%

A Transistor Operations Model for Deep Learning Energy Consumption Scaling Law

Tsourdos

Guo

2024

IEEE Trans. Artif. Intell.

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“…Calore et al measure power using tx2mon for computations running on a single ThunderX2 node to calculate energy efficiency of Lattice Boltzmann and Lattice quantum chromodynamics applications, but their experiments do not vary the frequency of the processor. 38 On the more memory bound of the two applications, they observe roughly half the energy usage along with superior performance using ThunderX2 compared to Intel Skylake. For the more compute bound of the two applications, they observe similar energy usage and about 20% less performance.…”

Section: Related Workmentioning

confidence: 99%

“…They obtained board level and processor hardware counter measurements during executions of the PARSEC and Splash‐2 benchmarks to show that energy costs of cache coherency are reasonable. Calore et al measure power using tx2mon for computations running on a single ThunderX2 node to calculate energy efficiency of Lattice Boltzmann and Lattice quantum chromodynamics applications, but their experiments do not vary the frequency of the processor 38 . On the more memory bound of the two applications, they observe roughly half the energy usage along with superior performance using ThunderX2 compared to Intel Skylake.…”

Section: Related Workmentioning

confidence: 99%

Enabling power measurement and control on Astra: The first petascale Arm supercomputer

Grant

Hammond

Laros

et al. 2022

Concurrency and Computation

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Summary Astra, deployed in 2018, was the first petascale supercomputer to utilize processors based on the ARM instruction set. The system was also the first under Sandia's Vanguard program which seeks to provide an evaluation vehicle for novel technologies that with refinement could be utilized in demanding, large‐scale HPC environments. In addition to ARM, several other important first‐of‐a‐kind developments were used in the machine, including new approaches to cooling the datacenter and machine. This article documents our experiences building a power measurement and control infrastructure for Astra. While this is often beyond the control of users today, the accurate measurement, cataloging, and evaluation of power, as our experiences show, is critical to the successful deployment of a large‐scale platform. While such systems exist in part for other architectures, Astra required new development to support the novel Marvell ThunderX2 processor used in compute nodes. In addition to documenting the measurement of power during system bring up and for subsequent on‐going routine use, we present results associated with controlling the power usage of the processor, an area which is becoming of progressively greater interest as data centers and supercomputing sites look to improve compute/energy efficiency and find additional sources for full system optimization.

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“…However, its short 128-bit vector size makes it less suitable for applications requiring intensive computation [17]. Despite this limitation, its high memory bandwidth makes it well-suited for memory-intensive applications [18].…”

Section: Arm-based Hpcmentioning

confidence: 99%

First Steps towards Efficient Genome Assembly on ARM-Based HPC

Poje,

Brcic,

Knezovic

et al. 2023

Electronics

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Exponential advances in computational power have fueled advances in many disciplines, and biology is no exception. High-Performance Computing (HPC) is gaining traction as one of the essential tools in scientific research. Further advances to exascale capabilities will necessitate more energy-efficient hardware. In this article, we present our efforts to improve the efficiency of genome assembly on ARM-based HPC systems. We use vectorization to optimize the popular genome assembly pipeline of minimap2, miniasm, and Racon. We compare different implementations using the Scalable Vector Extension (SVE) instruction set architecture and evaluate their performance in different aspects. Additionally, we compare the performance of autovectorization to hand-tuned code with intrinsics. Lastly, we present the design of a CPU dispatcher included in the Racon consensus module that enables the automatic selection of the fastest instruction set supported by the utilized CPU. Our findings provide a promising direction for further optimization of genome assembly on ARM-based HPC systems.

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ThunderX2 Performance and Energy-Efficiency for HPC Workloads

Cited by 15 publications

References 34 publications

A Transistor Operations Model for Deep Learning Energy Consumption Scaling Law

A Transistor Operations Model for Deep Learning Energy Consumption Scaling Law

Enabling power measurement and control on Astra: The first petascale Arm supercomputer

First Steps towards Efficient Genome Assembly on ARM-Based HPC

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