The survivability of design-specific spare placement in FPGA architectures with high defect rates

Agarwal, Amit; Cong, Jason; Tagiku, Brian

doi:10.1145/2442087.2442104

Cited by 2 publications

(1 citation statement)

References 29 publications

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“…Even after built-in test and repair (BISTAR), it is conceivable that noncritical faults may have been inadvertently triggered during resource reallocation and may compromise normal operation. BISTAR will continue to feature in future FPGAs [41], configurable ASICs [42] and nanoscale electronics [43] and it has been suggested that BISTAR logic could be made available for runtime test or repair of logic [44] and interconnects [45].…”

Section: Topicmentioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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Section: Topicmentioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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A Fault-Aware Toolchain Approach for FPGA Fault Tolerance

Gupte

Vyas

Jones

2015

ACM Trans. Des. Autom. Electron. Syst.

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As the size and density of silicon chips continue to increase, maintaining acceptable manufacturing yields has become increasingly difficult. Recent works suggest that lithography techniques are reaching their limits with respect to enabling high yield fabrication of small-scale devices, thus there is an increasing need for techniques that can tolerate fabrication time defects. One candidate technology to help combat these defects is reconfigurable hardware. The flexible nature of reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), makes it possible for them to route around defective areas of a chip after the device has been packaged and deployed into the field. This work presents a technique that aims to increase the effective yield of FPGA manufacturing by re-claiming a portion of chips that would be ordinarily classified as unusable. In brief, we propose a modification to existing commercial toolchain flows to make them fault aware. A phase is added to identify faults within the chip. The locations of these faults are then used by the toolchain to avoid faults during the placement and routing phase. Specifically, we have applied our approach to the Xilinx commercial toolchain flow and evaluated its tolerance to both logic and routing resource faults. Our findings show that, at a cost of 5--10% in device frequency performance, the modified toolchain flow can tolerate up to 30% of logic resources being faulty and, depending on the nature of the target application, can tolerate 1--30% of the device's routing resources being faulty. These results provide strong evidence that commercial toolchains not designed for the purpose of tolerating faults can still be greatly leveraged in the presence of faults to place and route circuits in an efficient manner.

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The survivability of design-specific spare placement in FPGA architectures with high defect rates

Cited by 2 publications

References 29 publications

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

A Fault-Aware Toolchain Approach for FPGA Fault Tolerance

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