The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

Korinth, Jens; Hofmann, Jaco; Heinz, Carsten; Koch, Andreas

doi:10.1007/978-3-030-17227-5_16

Cited by 29 publications

(10 citation statements)

References 12 publications

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“…This also applies to the hardware level: If a hardware module conforms to the TaPaSCo interface requirements, it can be used on any supported platform. Furthermore, TaPaSCo was designed to be easily extensible to new platforms: Within one year of TaPaSCo's initial presentation in [43], the number of supported platforms has doubled from seven to fourteen. The list of of supported platforms ranges from small embedded boards using Zynq devices, up to high-performance PCIe-based expansion cards with large UltraScale+ FPGA devices.…”

Section: Portabilitymentioning

confidence: 99%

The TaPaSCo Open-Source Toolflow

Heinz

Hofmann

Korinth

et al. 2021

J Sign Process Syst

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The integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

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Section: Portabilitymentioning

confidence: 99%

The TaPaSCo Open-Source Toolflow

Heinz

Hofmann

Korinth

et al. 2021

J Sign Process Syst

Self Cite

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“…As shown in the table, there are currently a small number of other frameworks that adhere to these criteria. TaPaSCo [20] allows designers to easily set up systems that perform several hardware-accelerated tasks in parallel. It is in some sense complementary to Fletcher, since (as will be discussed again later) Fletcher provides an AXI4 top level for memory access, alongside an AXI4lite for the control path of the kernel, exactly fitting the integration style of TaPaSCo's processing elements.…”

Section: Related Workmentioning

confidence: 99%

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Peltenburg

Straten

Brobbel

et al. 2021

J Sign Process Syst

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As big data analytics systems are squeezing out the last bits of performance of CPUs and GPUs, the next near-term and widely available alternative industry is considering for higher performance in the data center and cloud is the FPGA accelerator. We discuss several challenges a developer has to face when designing and integrating FPGA accelerators for big data analytics pipelines. On the software side, we observe complex run-time systems, hardware-unfriendly in-memory layouts of data sets, and (de)serialization overhead. On the hardware side, we observe a relative lack of platform-agnostic open-source tooling, a high design effort for data structure-specific interfaces, and a high design effort for infrastructure. The open source Fletcher framework addresses these challenges. It is built on top of Apache Arrow, which provides a common, hardware-friendly in-memory format to allow zero-copy communication of large tabular data, preventing (de)serialization overhead. Fletcher adds FPGA accelerators to the list of over eleven supported software languages. To deal with the hardware challenges, we present Arrow-specific components, providing easy-to-use, high-performance interfaces to accelerated kernels. The components are combined based on a generic architecture that is specialized according to the application through an extensive infrastructure generation framework that is presented in this article. All generated hardware is vendor-agnostic, and software drivers add a platform-agnostic layer, allowing users to create portable implementations.

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“…At present, there have been many achievements, but mainly for specific research directions and areas. [14][15][16] For this reason, the Par4All automatic parallel software package was designed and developed by the HPC Project Lab in France, which has undoubtedly brought automatic parallel code generation technology to a new level of practicality. Par4All is an open-source automatic parallel compilation and optimization module that can automatically generate OpenMP/CUDA/OpenCL parallel code files in the C or Fortran languages.…”

mentioning

confidence: 99%

Preliminary study on the automatic parallelism optimization model for image enhancement algorithms based on Intel's® Xeon Phi

Huang

Yang

Jian

et al. 2021

Concurrency and Computation

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In unmanned aerial vehicle (UAV) image-processing applications, one needs to implement different parallel image-enhancement algorithms on several high-performance computing platforms utilizing various programming models. To speed up the parallelization procedure and improve its efficiency, the automatic parallel software package, Par4All, is applied in this work. We find that the performance of the original automatic parallelization algorithm produced with Par4All is inefficient. To resolve this problem, we propose different optimization approaches for Par4All based on Intel®'s Xeon Phi high-performance computing platform that are based on the structural features of the image-enhancement algorithms, which can further optimize the original parallel algorithm. These approaches mainly include: (1) Par4All automatic parallel search module optimization, (2) dynamic thread setting optimization, and (3) the collaborative parallelization of both CPU and many integrated core (MIC) processors.According to the results of the comparison experiments involving different algorithms, it is shown that the proposed optimization approaches for these kinds of algorithms can significantly improve the performance of automatic parallel algorithms. The acceleration ratio increases approximately by 30%, 70%, and 80% for the multiscale Retinex, Gaussian-filtering and median-filtering algorithms, respectively. As continuation and deepening of our previous research work, this research has the potential to be beneficial for other researchers in image-processing applications with image-enhancement algorithms. K E Y W O R D Sautomatic parallelism, image-enhancement algorithms, Par4All, Intel® Xeon Phi, unmanned aerial vehicles INTRODUCTIONAs mentioned by References 1, it is known that some image-enhancement algorithms, for example, median filtering, Gaussian filtering, wavelet transform, and the multiscale Retinex (MSR) algorithm, are used when preprocessing large amounts of unmanned aerial vehicle (UAV) remote-sensing (RS) images to solve the problems of poor clarity, insufficient contrast and low adaptability. In addition, many-cores computing platforms, e.g., graphics processing units (GPUs) and many integrate cores (MICs), have been involved in the development of some parallel algorithms to speed up the processing times 2 ; such approaches are expected to become mainstream in the near future. Experimental results have shown that parallelized algorithms can significantly improve computation speed and provide better acceleration efficiency. [3][4][5] Usually, there are different kinds of serial

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The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

Cited by 29 publications

References 12 publications

The TaPaSCo Open-Source Toolflow

The TaPaSCo Open-Source Toolflow

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Preliminary study on the automatic parallelism optimization model for image enhancement algorithms based on Intel's® Xeon Phi

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