The Temporal Logic of Reactive and Concurrent Systems

Abstract. We propose two expressive and complementary techniques for the verification of safety properties of infinite-state BIP models. Both our techniques deal with the full BIP specification, while the existing approaches impose considerable restrictions: they either verify finite-state systems or they do not handle the transfer of data on the interactions and priorities. Firstly, we propose an instantiation of the ESST (Explicit Scheduler Symbolic Thread) framework to verify BIP models. The key insight is to apply symbolic reasoning to analyze the behavior of the system described by the BIP components, and an explicit-state search to analyze the behavior of the system induced by the BIP interactions and priorities. The combination of symbolic and explicit exploration techniques allow to benefit from abstraction, useful when reasoning about data, and from partial order reduction, useful to mitigate the state space explosion due to concurrency. Secondly, we propose an encoding from a BIP model into a symbolic, infinitestate transition system. This technique allows us to leverage the state of the art verification algorithms for the analysis of infinite-state systems. We implemented both techniques and we evaluated their performance against the existing approaches. The results show the effectiveness of our approaches with respect to the state of the art, and their complementarity for the analysis of safe and unsafe BIP models.

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“…The semantic of an STS can be given in terms of an explicit transition systems (see for example [26]). …”

Section: Encoding Bip Into Transition Systemmentioning

confidence: 99%

Formal Verification of Infinite-State BIP Models

Bliudze

Cimatti

Jaber

et al. 2015

Lecture Notes in Computer Science

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“…The Synchronous Transition System (STS) formalism, introduced by Manna and Pnueli [13] models a synchronous system s as a couple (P s , B s ) where P s is the set of the I/O ports and state variables of the system and B s is the set of the traces admitted by the system; a trace is an infinite sequence of states and a state is a valuation of all the element of P s . If P is a set of ports, we denote by σ(P ) a valuation of the ports in the set P and by Λ(P ) the set of the possible valuations of the ports in P.…”

Section: A Sts and Sts*mentioning

confidence: 99%

Distributing synchronous systems with modular structure

Zennaro

Sengupta

2004

2004 43rd IEEE Conference on Decision and Control (CDC) (IEEE Cat. No.04CH37601)

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Abstract-Synchronous programs were introduced to simplify the development of reactive systems hiding the complexity and indeterminism of the interleaving while taking full advantage of possible concurrency. The introduction of communication networks enabled the creation of distributed systems presenting the programmer with a new burden of interleaving and non determinism due to the asynchronous communication medium. Again this complexity should be hidden from the user while taking full advantage of the possible concurrency to improve performance. Many algorithms for the automatic distributions of synchronous programs have been proposed so far, but they are not suitable for large scale system because they do not preserve the compositionality of the original code: the modularity of the synchronous program is lost. As a result the subsystems are not re-usable and a small local change results in the recompilation and re-distribution of the overall system. This solution is cumbersome and unpractical in many real-world applications. In this paper we introduce an algorithm for the distribution of synchronous programs that preserves the modularity and allows separate compilation and subsystem re-use.

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“…As is often the case with tableaus for temporal logics, e.g., [7,12], a state of the tableau consists of a set of formulas that are supposed to hold along all paths leaving the state. We propose therefore to define a reduced tableau of ACTL formulas consisting of less states and transitions but accepting precisely the models of the formulas.…”

Section: Compositional Verification and Environment Synthesismentioning

confidence: 99%

Compositional Verification of a Switch Fabric from Nortel Networks

Peng

Tahar

Mokhtari

2003

Formal Methods and Software Engineering

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With the development of ASIC designs, simulation cannot cover all the corner cases in a complicated design. Model checking is a fully automatic approach to verify a finite state machine against its temporal specifications. However, its application is limited by the size of the system to be verified. Compositional verification and model reduction are two possible methods to tackle this problem. In this paper, we propose a verification framework based on assumeguarantee compositional model checking, where we can apply model checking to do exhaustive verification at the module level and conduct global properties via compositional reasoning. In this framework, temporal specifications are synthesized into Verilog modules. In case a module under verification is beyond the capability of model checking, the proposed model reduction algorithm is used. We implemented the framework on top of the VIS tool and applied it on an ATM switch fabric from Nortel Networks.

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The Temporal Logic of Reactive and Concurrent Systems

Cited by 2,251 publications

References 0 publications

Formal Verification of Infinite-State BIP Models

Formal Verification of Infinite-State BIP Models

Distributing synchronous systems with modular structure

Compositional Verification of a Switch Fabric from Nortel Networks

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