The TM3270 Media-Processor

Waerdt, Jan-Willem van de; Vassiliadis, S.; Das, Sanjeev; Mirolo, Sebastian; Yen, Chris; Zhong, Bill; Basto, Carlos; Itegem, Jean-Paul van; Amirtharaj, Dinesh; Kalra, Kulbhushan; Rodríguez, Pedro; Antwerpen, Hans van

doi:10.1109/micro.2005.35

Cited by 56 publications

(32 citation statements)

References 18 publications

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“…The TM3270 [12] is a VLIW-based media-processor based on the Trimedia architecture. It addresses the requirements of multi-standard video processing at standard resolution and the associated audio processing requirements for the consumer market.…”

Section: Experimental Methodologymentioning

confidence: 99%

A Highly Scalable Parallel Implementation of H.264

Azevedo

Juurlink

Meenderinck

et al. 2011

Lecture Notes in Computer Science

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Abstract. Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to a large number of cores. The algorithm exploits the fact that independent macroblocks (MBs) can be processed in parallel, but whereas a previous approach exploits only intra-frame MB-level parallelism, our algorithm exploits intra-frame as well as inter-frame MB-level parallelism. It is based on the observation that inter-frame dependencies have a limited spatial range. The algorithm has been implemented on a many-core architecture consisting of NXP TriMedia TM3270 embedded processors. This required to develop a subscription mechanism, where MBs are subscribed to the kick-off lists associated with the reference MBs. Extensive simulation results show that the implementation scales very well, achieving a speedup of more than 54 on a 64-core processor, in which case the previous approach achieves a speedup of only 23. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the frame latency might increase. Scheduling policies to address these drawbacks are also presented. The results show that these policies combat memory and latency issues with a negligible effect on the performance scalability. Results analyzing the impact of the memory latency, L1 cache size, and the synchronization and thread management overhead are also presented. Finally, we present performance requirements for entropy (CABAC) decoding.

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Section: Experimental Methodologymentioning

confidence: 99%

A Highly Scalable Parallel Implementation of H.264

Azevedo

Juurlink

Meenderinck

et al. 2011

Lecture Notes in Computer Science

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“…Reducing the energy dissipation of the register file has always been considered important in improving processor energy efficiency [10,32] within a typical single-issue RISC processor is dissipated by the register file, and an even higher percentage for processors that exploit more instruction-level or data-level parallelism [9,30,32]. Earlier work has shown that optimizing the bypassing network can reduce this large energy usage [6].…”

Section: Related Workmentioning

confidence: 99%

A Low-Energy Wide SIMD Architecture with Explicit Datapath

Waeijen

She

Corporaal

et al. 2014

J Sign Process Syst

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Energy efficiency has become one of the most important topics in computing. To meet the ever increasing demands of the mobile market, the next generation of processors will have to deliver a high compute performance at an extremely limited energy budget. Wide single instruction, multiple data (SIMD) architectures provide a promising solution, as they have the potential to achieve high compute performance at a low energy cost. We propose a configurable wide SIMD architecture that utilizes explicit datapath techniques to further optimize energy efficiency without sacrificing computational performance. To demonstrate the efficiency of the proposed architecture, multiple instantiations of the proposed wide SIMD architecture and its automatic bypassing counterpart, as well as a baseline RISC processor, are implemented. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve an average of 206 times speed-up and reduces the total energy dissipation by 48.3% on average and up to 94%, compared to a reduced instruction set computing (RISC) processor. Compared to the corresponding SIMD architecture with automatic bypassing, an average of 64% of all register file accesses is avoided by the 128-PE, explicitly bypassed SIMD. For total energy dissipation, an average of 27.5%, and maximum of 43.0%, reduction is achieved.

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“…The Trimedia processor series is developed by Phillips. Trimedia TM3270 is Very Long Instruction Word (VLIW) based architecture [13]. This processor can support up to 7 billon operations per second.…”

Section: Related Workmentioning

confidence: 99%

Comparison of Three Smart Camera Architectures for Real-Time Machine Vision System

Malik

Thörnberg

Kumar

2013

International Journal of Advanced Robotic Systems

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This paper presents a machine vision system for real-time computation of distance and angle of a camera from a set of reference points located on a target board. Three different smart camera architectures were explored to compare performance parameters such as power consumption, frame speed and latency. Architecture 1 consists of hardware machine vision modules modeled at Register Transfer (RT) level and a soft-core processor on a single FPGA chip. Architecture 2 is commercially available software based smart camera, Matrox Iris GT. Architecture 3 is a two-chip solution composed of hardware machine vision modules on FPGA and an external microcontroller. Results from a performance comparison show that Architecture 2 has higher latency and consumes much more power than Architecture 1 and 3. However, Architecture 2 benefits from an easy programming model. Smart camera system with FPGA and external microcontroller has lower latency and consumes less power as compared to single FPGA chip having hardware modules and soft-core processor.

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The TM3270 Media-Processor

Cited by 56 publications

References 18 publications

A Highly Scalable Parallel Implementation of H.264

A Highly Scalable Parallel Implementation of H.264

A Low-Energy Wide SIMD Architecture with Explicit Datapath

Comparison of Three Smart Camera Architectures for Real-Time Machine Vision System

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