The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers

Elmore, W. C.

doi:10.1063/1.1697872

Cited by 1,521 publications

(610 citation statements)

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“…For each sink we compute the delay and slew using SPICE simulator and measure the relative error of the appropriate metric to the SPICE result. The simulation goal is twofold: first, to compute our delay metric (WbD) with Kahng-Muddu Model (KM) [9] and Elmore Delay (ED [1] and second, to assess our slew metric (WbS) in comparison to [1] and [11]. We call these metrics as ES and BkS, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…So efficient and accurate computation of the interconnect delay has become increasingly critical. On the other hand very few approaches [1] [11] have been proposed for interconnect slew calculation. In the nanotechnology age, as ultra deep sub-micron effects continue to wreak havoc on the integrity of the signal, so efficient and accurate computation of the slew metric has become critical.…”

Section: Introductionmentioning

confidence: 99%

“…The Elmore Delay [1] which is the first moment of the impulse response provides standard delay estimation for performance driven design applications. Elmore approximated the median of the impulse response (50% delay of the step response) to the mean of the impulse response by noting the similarity between non-negative impulse response and probability density functions.…”

Section: Introductionmentioning

confidence: 99%

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Delay and Slew Metrics for On-Chip VLSI Interconnect

Kar¹,

Chattaraj²,

Chandra³

et al. 2010

IJCEE

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Delay and Slew Metrics for On-Chip VLSI Interconnect

Kar¹,

Chattaraj²,

Chandra³

et al. 2010

IJCEE

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“…the area under the voltage curve, when the voltages are initialized as v i 0 = 1 (see Elmore 1948). The Elmore delay D i is a reasonable measure of the time it takes the voltage at node i to decay, from an initial value of one.…”

Section: Rc Tree Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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“…5. The signal delay can be approximately calculated by Elmore delay model [5], which is a widely used delay model, as shown in (1).…”

Section: Problem Definitionmentioning

confidence: 99%

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

Kobayashi¹,

Minami²

2013

IEICE Trans. Inf. & Syst.

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SUMMARYAs the LSI process technology advances and the gate size becomes smaller, the signal delay on interconnect becomes a significant factor in the signal path delay. Also, as the size of interconnect structure becomes smaller, the interconnect process variations have become one of the dominant factors which influence the signal delay and thus clock skew. Therefore, controlling the influence of interconnect process variations on clock skew is a crucial issue in the advanced process technologies. In this paper, we propose a method for minimizing clock skew fluctuations caused by interconnect process variations. The proposed method identifies the suitable balance of clock buffer size and wire length in order to minimize the clock skew fluctuations caused by the interconnect process variations. Experimental results on test circuits of 28 nm process technology show that the proposed method reduces the clock skew fluctuations by 30-92% compared to the conventional method.

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The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers

Cited by 1,521 publications

References 1 publication

Delay and Slew Metrics for On-Chip VLSI Interconnect

Delay and Slew Metrics for On-Chip VLSI Interconnect

Digital Circuit Optimization via Geometric Programming

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations

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