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Slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn reduces the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits. In this paper we have proposed an accurate and efficient model to compute the slew metric of on chip interconnect of high speed CMOS VLSI deigns. Our slew metric is based on the Nakagami-M distribution function. Comparison of simulation results with other established models justifies the accuracy of our slew approach.