Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function

Kar, Rajib; Chattaraj, A.; Chandra, Aniruddha; Mal, Ashis Kumar; Bhattacharjee, A. K.

doi:10.1109/iciinfs.2008.4798399

Cited by 4 publications

(1 citation statement)

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“…(1) We compared the delays obtained from SPICE, Weibull Distribution (WD) [11] and Gamma Distribution (GD) [12] with those found using the inverse gamma approximation (IGD). The results for the 50% delay are summarized in Table I.…”

Section: Simulation Resultsmentioning

confidence: 99%

Delay Estimation for Global RC Interconnect UsingInverse Gamma Distribution Function

Maheshwari¹

2012

IJIEE

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In this paper, we present an efficient model for onchip interconnects delay analysis. Several approaches have already been proposed for approximating the interconnect delay accurately and efficiently. Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression to the moment matching methods which create reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an accurate approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees, it is demonstrated that inverse gamma functions provide a probably stable approximation. The accuracy of the proposed model is justified with the results obtained from that of SPICE simulations. Index Terms-Delay Calculation, inverse gamma distribution, moment matching, on-chip interconnect; probability distribution function.

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Section: Simulation Resultsmentioning

confidence: 99%